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參數(shù)資料
| 型號(hào)： | M27V101-100K1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 128Kb x 8 Low Voltage UV EPROM and OTP EPROM |
| 中文描述： | 1兆位的128KB × 8低壓紫外線可擦寫(xiě)可編程只讀存儲(chǔ)器和OTP存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 104K |
| 代理商： | M27V101-100K1TR |
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M27V101
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70
°
C or –40 to 85
°
C; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°
C or –40 to 85
°
; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurament conditions.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±
10
μ
A
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±
10
μ
A
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
≤
3.6V
15
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
– 0.2V, V
CC
≤
3.6V
20
μ
A
I
PP
Program Current
V
PP
= V
CC
10
μ
A
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –400
μ
A
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
Vcc – 0.7V
V
Symbol
Alt
Parameter
Test Condition
M27V101
Unit
- 90
(3)
-100
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
90
100
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
90
100
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
45
50
ns
t
EHQZ(2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
30
0
30
ns
t
GHQZ(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
30
0
30
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
0
0
ns
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
μ
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7
μ
F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purposeof the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M27V101-100K6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x 8 Low Voltage UV EPROM and OTP EPROM |
| M27V101-100N1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x 8 Low Voltage UV EPROM and OTP EPROM |
| M27V101-100N6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x 8 Low Voltage UV EPROM and OTP EPROM |
| M27V101-120B1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x 8 Low Voltage UV EPROM and OTP EPROM |
| M27V101-120B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x 8 Low Voltage UV EPROM and OTP EPROM |
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