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參數(shù)資料
| 型號(hào)： | M28C16-20NS6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Kbit 2Kb x8 Parallel EEPROM |
| 中文描述： | 16千位2KB的x8并行的EEPROM |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大?。?/td> | 134K |
| 代理商： | M28C16-20NS6 |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
AI01520
ADDRESS
LATCH
A6-A10
(Page Address)
X
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPPGEN
RESET
SENSE AND DATA LATCH
I/O BUFFERS
E
G
W
PAGE
LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Figure 3. Block Diagram
Write
Write operations are initiated when both W and E
arelow andG is high.TheM28C16A/17Asupports
bothE and W controlledwritecycles.The Address
is latchedby the falling edge of E or W which ever
occurslast and the Data on therising edge of E or
W which ever occurs first. Once initiated the write
operationis internally timed until completion.
Page Write
Page write allows up to 32 bytes to be consecu-
tively latched into the memory prior to initiating a
DQ7
DQ6 DQ5 DQ4 DQ3 DQ2
DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 4. StatusBit Assignment
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
programming cycle. All bytes must be located in a
single page address, that is A5 - A10 must be the
samefor all bytes. The page write can be initiated
during any bytewrite operation.
Following the first byte write instruction the host
may send another addressand dataup to a maxi-
mumof t
WHWH
afterthe risingedge ofEorWwhich
ever occurs first. If a transition of E or W is not
detected within t
WHWH
, the internal programming
cycle will start.
Microcontroller Control Interface
The M28C16A/17A provides two write operation
status bits and one status pin that can be used to
minimize thesystemwritecycle.Thesesignalsare
available on the I/O port bits DQ7 or DQ6 of the
memory during programming cycle only, or as the
RB signal on a separatepin.
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
OPERATION
(cont’d)
4/19
M28C16A, M28C17A
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| M28C16-20WBS6 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16 Kbit 2Kb x8 Parallel EEPROM |
| M28C16-20WKA6 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16 Kbit 2Kb x8 Parallel EEPROM |
| M28C16-20WMS6 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16 Kbit 2Kb x8 Parallel EEPROM |
| M28C16-20WNS6 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16 Kbit 2Kb x8 Parallel EEPROM |
| M28C16-250K1T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16K (2K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION |
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