參數(shù)資料
型號: M28W800B100N1T
廠商: NUMONYX
元件分類: PROM
英文描述: 512K X 16 FLASH 3V PROM, 100 ns, PDSO48
封裝: 12 X 20 MM, PLASTIC, TSOP-48
文件頁數(shù): 4/40頁
文件大?。?/td> 284K
代理商: M28W800B100N1T
M28W800T, M28W800B
12/40
BLOCK PROTECTION
Two parameter blocks can be protected against
Program or Erase to ensure extra data security.
For M28W800T, the blocks from address 7E000h
to 7FFFFh can be protected. For M28W800B, the
blocks from address 00000h to 01FFFh can be
protected.
Unprotected
blocks
can
be
pro-
grammed or erased.
WP tied to VIL protects the two lockable blocks.
Any program or erase operation on protected
blocks is aborted. The Status Register tracks
when the event occurs.
WP tied to VIH unprotects all the blocks that can be
protect. Table 9 defines the protection methods.
RP tied to VIL protects all blocks.
POWER CONSUMPTION
The M28W800 place itself in one of four different
modes depending on the status of the control sig-
nals: Active Power, Automatic Power Savings,
Standby and Power Down define decreasing lev-
els of current consumption. These allow the mem-
ory power to be minimised, in turn decreasing the
overall system power consumption.
As different recovery time are linked to the differ-
ent modes, please refer to the AC timing table to
design your system.
Active Power
When E is at VIL and RP is at VIH, the device is in
active mode. Refer to DC Characteristics to get
the values of the current supply consumption.
Automatic Stand-by
Automatic Stand-by provides a low power con-
sumption state during read mode.
Following a read operation, after a delay close to
the memory access time, the device enters Auto-
matic Stand-by: the Supply Current is reduced to
ICC1 values. The device keeps the last output data
stable, till a new location is accessed.
Stand-by
Refer to the Device Operations section.
Power Down
Refer to the Device Operations section.
Power Up
The Supply voltage VDD and the Program Supply
voltage VPP can be applied in any order. The
Figure 3. OTP Memory Area Address Table
AI02545
00000h
OTP word # 0
OTP word # 255
000FFh
memory Command Interface is reset on power up
to Read Memory Array, but a negative transition of
Chip Enable E or a change of the addresses is re-
quired to ensure valid data outputs. Care must be
taken to avoid writes to the memory when VDD is
above VLKO and VPP powers up first. Writes can
be inhibited by driving either E or W to VIH. The
memory is disabled until RP is up to VIH.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling, each device in a system should
have the VDD and VPP rails decoupled with a 0.1F
capacitor close to the VDD and VPP pins. The PCB
trace widths should be sufficient to carry the re-
quired VPP program and erase currents.
OTP MEMORY AREA
M28W800 features an additional "One Time Pro-
grammable" Memory Area. This feature is ob-
tained by means of an OTP Block of 256 word,
which can be programmed once and cannot be
erased, thus useful to store permanent data. This
OTP memory area can be programmed and ad-
dressed in Read Mode by the customer through
two dedicated commands. Refer to the Program
OTP Area (PDO) and Read OTP Area (RDO) in-
structions to properly write and read the OTP
memory block.
The OTP Memory Area is organized as 256 x 16
bits as shown in the OTP Address Table, Figure 3.
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