參數(shù)資料
型號: M29W800AB100N5T
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
中文描述: 8兆1兆x8或512KB的x16插槽,引導(dǎo)塊低壓單電源閃存
文件頁數(shù): 18/33頁
文件大?。?/td> 234K
代理商: M29W800AB100N5T
M29W800AT, M29W800AB
18/33
Table 18. Write AC Characteristics, W Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol
Alt
Parameter
M29W800AT / M29W800AB
Unit
100
120
V
CC
= 2.7V to 3.6V
CL = 30pF
V
CC
= 2.7V to 3.6V
CL = 30pF
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
100
120
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
DVWH
t
DS
Input Valid to Write Enable High
45
50
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
PHPHH(1, 2)
t
VIDR
RP Rise Time to V
ID
500
500
ns
t
PHWL(1)
t
RSP
RP High to Write Enable Low
4
4
μ
s
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
t
WHRL(1)
t
BUSY
Program Erase Valid to RB Delay
90
90
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
30
30
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
45
50
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
35
50
ns
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
and Read/Reset RD instructions. Data Polling bit
DQ7 returns ’0’ while the erasure is in progress
and ’1’ when it has completed. The Toggle bit DQ2
and DQ6 toggle during the erase operation. They
stop when erase is completed. After completion
the Status Register bit DQ5 returns ’1’if there has
been an erasefailure. In such a situation, theTog-
gle bit DQ2 can be used to determine which block
is notcorrectly erased. In the caseof erase failure,
a Read/ResetRD instruction is necessary inorder
to reset the P/E.C.
Chip Erase (CE) Instruction.
This
uses six write cycles. The Erase Set-up command
80h is written to address AAAh in the Byte-wide
configuration or the address 555h in the Word-
instruction
wide configuration on the third cycle after the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after an-
other two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy-
cles are wrong, the instruction aborts and the de-
vice is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh.
Read operations afterthe sixth rising edge of W or
E output the Status Register bits. During the exe-
cution of the erase by the P/E.C., Data Polling bit
DQ7 returns ’0’,then ’1’oncompletion. TheToggle
bits DQ2 and DQ6 toggle during erase operation
and stop when erase is completed. After comple-
tion the Status Register bit DQ5 returns ’1’if there
has been an Erase Failure.
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