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參數(shù)資料
| 型號： | M29W800AB100N5T |
| 廠商： | 意法半導體 |
| 英文描述： | 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory |
| 中文描述： | 8兆1兆x8或512KB的x16插槽，引導塊低壓單電源閃存 |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 234K |
| 代理商： | M29W800AB100N5T |
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M29W800AT, M29W800AB
6/33
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A18).
The address inputs
for thememory array arelatched duringa write op-
eration on the falling edge at Chip Enable E or
Write Enable W. In Word-wide organisation the
address lines are A0-A18, in Byte-wide organisa-
tion DQ15A–1 acts as an additional LSB address
line. When A9 is raised to V
ID
, eithera Read Elec-
tronic Signature Manufacturer or Device Code,
Block ProtectionStatus ora Write BlockProtection
or BlockUnprotection is enableddepending onthe
combination oflevels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7).
These
Outputs are used in the Byte-wide and Word-wide
organisations. Theinput isdata to be programmed
in the memory array ora command to be written to
the C.I.Both are latched on the rising edge ofChip
Enable E or Write Enable W. The output is data
from the Memory Array, the Electronic Signature
Manufacturer or Device codes, the Block Protec-
tion Status or the Status register Data Polling bit
DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
DQ5 orthe Erase Timer bit DQ3. Outputs arevalid
when Chip Enable E and Output Enable G are ac-
tive. The output is high impedance when the chip
is deselected or the outputs are disabled and
when RP is at a Low level.
Data Input/Outputs (DQ8-DQ14 and DQ15A–
1).
These Inputs/Outputs are additionally used in
the Word-wide organisation. When BYTE is High
DQ8-DQ14 and DQ15A–1 act as the MSB of the
Data Input or Output, functioning as described for
DQ0-DQ7 above, and DQ8-DQ15 are ’don’t care’
for command inputs or status outputs. When
BYTE is Low, DQ0-DQ14 are high impedance,
DQ15A–1 is the Address A–1 input.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders andsense amplifiers.E High deselects the
memory and reduces the power consumption to
the stan-by level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at a low level. The Chip
Enable must be forced to V
ID
during theBlock Un-
protection operation.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is High the outputs are High im-
pedance. G must be forced to V
ID
level during
Block Protection and Unprotection operations.
Inputs/
Write Enable (W).
This input controls writing to
the Command Register and Address and Data
latches.
Byte/WordOrganization Select (BYTE).
The BYTE
input selects the output configuration for the de-
vice: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTE is Low, the Byte-wide mode is
selected and the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
Ready/Busy Output (RB).
Ready/Busy
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the de-
vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in-
struction. When RB is High, the device is ready for
any Read, Program or Erase operation. The RB
will also be High when the memory is put in Erase
Suspend or Stan-by modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP to
V
IL
for at least t
PLPX
. When the reset pulse is giv-
en, if the memory is in Read or Stan-by modes, it
will be available for new operations in t
PHEL
after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take t
PLYH
during which the RB signal will be held
at V
IL
. Theend of the memory reset will beindicat-
ed by the rising edge of RB. A hardware reset dur-
ing an Erase or Program operation will corrupt the
data being programmed or the sector(s) being
erased. See Tables 15, 16, and Figure 11.
Temporary block unprotection is made by holding
RP at V
ID
. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from V
IH
to V
ID
must slower than t
PH-
PHH
. See Tables 17, 18, and Figure 11. When RP
is returned from V
ID
to V
IH
all blocks temporarily
unprotected will be again protected.
V
CC
Supply Voltage.
The power supply for all
operations (Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
is
an
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相關(guān)代理商/技術(shù)參數(shù) |
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| M29W800AB100N6 | 功能描述:閃存 1Mx8 or 512Kx16 100n RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W800AB120M1 | 功能描述:閃存 1Mx8 or 512Kx16 120n RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W800AB120N1 | 功能描述:閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M29W800AB-120N1 | 制造商:STMicroelectronics 功能描述: |
| M29W800AB120N6 | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 8MBIT 1MX8/512KX16 120NS 48TSOP - Trays |
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