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參數(shù)資料
| 型號： | M30218MC-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 12/161頁 |
| 文件大?。?/td> | 2043K |
| 代理商： | M30218MC-XXXXFP |
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109
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O2
Figure GA-8. SBUSY2 Input Operation (2)
Figure GA-7. SBUSY2 Input Operation (1)
(2) SBUSY2 input signal
The SBUSY2 input is a signal requested to stop of transmission/reception from the serial transfer des-
tination.
When the internal synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L”
___________
level signal into the SBUSY2 input) in the initial status [serial I/O initialization bit (bit 4 of address
____________
034216) = “0”]. When a “L” level signal into the SBUSY2 ( or “H” on SBUSY2 ) input for 1.5 cycles or more
of transfer clock, transfer clocks are output from SCLK2i (i = 1, 2), and transmit/receive operation is
____________
started. When SBUSY2 input is driven “H” (or SBUSY2 input is driven “L”) during transmit/receive
operation, the transfer clock being output from SCLK2i (i = 1, 2) remains active until after the system
finishes sending or receiving the designated number of bits, without stopping the transmit/receive
operation immediately. The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic
transfer serial I/O is 8 bits.
Internal clock
"1"
"0"
"H"
"L"
Tc
D0
D1
D2
D3
D4
D5
D6
D7
1.5 cycle or more
Serial operation used SBUSY2 input
Operation mode
: 8-bit serial I/O mode
Transfer clock
: Internal synchronous clock
SBUSY2 input timing
: Each 1-byte data
Serial transfer status flag
(bit 5 at address 034416)
SCLK2i
(i = 1, 2)(output)
SOUT2
SBUSY2(input)
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
"1"
"0"
"H"
"L"
Note: The last output data
D0
D1
D2 D3
D4
D5
D6
D7
Invalid
Note
Serial operation used SBUSY2 input
Operation mode
: 8-bit serial I/O mode
Transfer clock
: External synchronous clock
SBUSY2 input timing
: Each 1-byte data
Serial transfer status flag
(bit 5 at address 034416)
SCLK2i
(i = 1, 2)(input)
SOUT2
SBUSY2(input)
High-impedance
When the external synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L”
___________
level signal into the SBUSY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216)
= “0”]. At this time, the transfer clock become invalid. The transfer clock become valid while a “L” level
___________
signal is input into the SBUSY2 input (or a “H” level signal into the SBUSY2 input) and transmit/receive
operation work.
___________
When changing the input values into the SBUSY2 (or SBUSY2) input at these operations, change them
when the transfer clock input is in a “H” state. When the high-impedance of the SOUT2 output is
selected by the SOUT2 pin control bit (bit 6 of address 034416), the SOUT2 becomes high-impedance,
___________
while a “H” level signal is input into the SBUSY2 input (or a “L” level signal into the SBUSY2 input.)
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