參數(shù)資料
型號(hào)： M30218MFCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 93/161頁
文件大?。?/td> 2043K
代理商： M30218MFCFP
37
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt sources without priority levels
7
Value set in the IPL
Watchdog timer
Other
Not changed
0
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table DD-6 is set in the IPL.
Table DD-6. Relationship between interrupts without interrupt priority levels and IPL
Stack pointer (SP) value
Interrupt vector address
16-Bit bust
8-Bit bus
Even
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
Table DD-5. Time required for executing the interrupt sequence
Reset
Indeterminate
1
2
34
56
78
9
10
11
12
13
14
15
16
17
18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Interrupt
information
Address
0000
Indeterminate
SP-2
SP-4
vec
vec+2
PC
BCLK
Address bus
Data bus
W
R
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction.
Time (b) is as shown in Table DD-5.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure DD-5. Time required for executing the interrupt sequence
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