參數(shù)資料
型號(hào): M30600E8-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 125/139頁(yè)
文件大小: 1782K
代理商: M30600E8-XXXGP
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
86
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
0V to AVCC (VCC)
Operating clock
AD
(Note 2) VCC = 5V
fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V
divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
Without sample and hold function
±3LSB
With sample and hold function (8-bit resolution)
±2LSB
With sample and hold function (10-bit resolution)
AN0 to AN7 input :
±3LSB
ANEX0 and ANEX1 input (including mode in which exter
nal operation amp is connected) :
±7LSB
VCC = 3V
Without sample and hold function (8-bit resolution)
±2LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin Without sample and hold function
8-bit resolution: 49
AD
cycles, 10-bit resolution: 59
AD
cycles
With sample and hold function
8-bit resolution: 28
AD
cycles, 10-bit resolution: 33
AD
cycles
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.35 shows the performance of the A-D converter. Figure 1.71 shows a block diagram of the A-D
converter, and Figures 1.72 and 1.73 show configurations of the A-D converter-related registers.
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the
AD
frequency to 250kHz min.
With the sample and hold function, set the
AD
frequency to 1MHz min.
Table 1.35. Performance of A-D converter
A-D conversion
start condition
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