參數(shù)資料
型號： M30600E8-XXXGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 83/139頁
文件大?。?/td> 1782K
代理商： M30600E8-XXXGP
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
48
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. Table 1.21 shows the DMAC specifications. Figure 1.33 shows a block
diagram of the DMAC. Figures 1.34 and 1.35 show the configuration of the registers used by the DMAC.
Item
Specification
No. of channels
2 (cycle steal method)
Transfer memory space
From any address in the 1M bytes space to a fixed address
From a fixed address to any address in the 1M bytes space
From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
________
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
Single transfer
The DMA enable bit is cleared and transfer ends when an underflow
occurs in the transfer counter
Repeat transfer
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is reloaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation timing When an underflow occurs in the transfer counter
DMA startup
Single transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Repeat transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Transfer starts when the DMA is requested after an underflow occurs in the transfer counter
DMA shutdown
When “0” is written to the DMA enable bit
When, in simple transfer mode, an underflow occurs in the transfer counter
When DMA transfer starts, the value of whichever of the source or destination pointer
that is set up as the forward pointer is reloaded into the forward address pointer. The
value in the transfer counter reload register is reloaded into the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Table 1.21. DMAC specifications
Forward address pointer and
reload timing for transfer
counter
Note: DMA transfer is not effective to any interrupt.
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