參數(shù)資料
型號(hào): M30624MGM-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 14/30頁
文件大?。?/td> 379K
代理商: M30624MGM-XXXGP
Mitsubishi microcomputers
M16C / 62M Group
(Low voltage version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
21
Read timing
Write timing
BCLK
CSi
ALE
RD
4ns.min
Hi–Z
DB
80ns.min
0ns.min
ADi
BHE
td(BCLK–WR)
60ns.max
th(BCLK–WR)
0ns.min
BCLK
CSi
td(BCLK–CS)
60ns.max
td(BCLK–AD)
ALE
th(BCLK–ALE)
th(BCLK–CS)
4ns.min
tcyc
0ns.min
th(WR–CS)
0ns.min
th(WR–AD)
ADi
BHE
td(BCLK–DB)
4ns.min
th(BCLK–DB)
td(DB–WR)
(tcyc–80)ns.min
0ns.min
th(WR–DB)
DBi
th(RD–AD)
0ns.min
td(BCLK–ALE)
60ns.max
tSU(DB–RD)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Measuring conditions :
VCC=3V
Input timing voltage : Determined with VIL=0.48V, VIH=1.5V
Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
WR,WRL,
WRH
td(BCLK–CS)
60ns.max
th(RD–CS)
tcyc
td(BCLK–AD)
60ns.max
th(BCLK–AD)
–4ns.min
th(BCLK–ALE)
60ns.max
td(BCLK–RD)
th(BCLK–RD) 0ns.min
tac2(RD–DB)
th(RD–DB)
0ns.min
th(BCLK–AD)
60ns.max
td(BCLK–ALE)
60ns.max
–4ns.min
80ns.max
th(BCLK–CS)
4ns.min
VCC = 3V
Figure 1.26.5. VCC=3V timing diagram (4)
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