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Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
22
Figure 1.5.1. Location of peripheral unit control registers (1)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016
004116
004216
004316
004416
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Wait control register (WCR)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
External data bus width control register (DS)
Main clock division register (MCD)
Address match interrupt register 2 (RMAD2)
Address match interrupt register 3 (RMAD3)
Emulator interrupt vector table register (EIAD)
Emulator interrupt detect register (EITD)
Emulator protect register (EPRR)
ROM areaset register (ROA)
Debug monitor area set register (DBA)
Expansion area set register 0 (EXA0)
Expansion area set register 1 (EXA1)
Expansion area set register 2 (EXA2)
Expansion area set register 3 (EXA3)
DRAM control register (DRAMCONT)
DRAM refresh interval set register (REFCNT)
Timer A1 interrupt control register (TA1IC)
UART0 transmit interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
UART0 receive interrupt control register (S0RIC)
UART2 transmit/NACK interrupt control register (S2TIC)
UART1 receive interrupt control register (S1RIC)
DMA2 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
Bus collision detection(UART3) interrupt control register (BCN3IC)
UART2 receive/ACK interrupt control register (S2RIC)
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A3 interrupt control register (TA3IC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A4 interrupt control register (TA4IC)
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
INT5 interrupt control register (INT5IC)
INT4 interrupt control register (INT4IC)
UART3 receive/ACK interrupt control register (S3RIC)
UART4 receive/ACK interrupt control register (S4RIC)
UART3 transmit/NACK interrupt control register (S3TIC)
UART4 transmit/NACK interrupt control register (S4TIC)
Exit priority register (RLVL)
UART1 transmit interrupt control register (S1TIC)
DMA1 interrupt control register (DM1IC)
DMA3 interrupt control register (DM3IC)
Bus collision detection(UART2) interrupt control register (BCN2IC)
Bus collision detection(UART4) interrupt control register (BCN4IC)
*
*As this register is used exclusively for debugger purposes, user cannot use this. Do not access to the register.
(The blank area is reserved and cannot be used by user.)