
Under
development
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
156
Selector
I/O
Timer
delay
UART2
Reception register
External clock
Arbitration
Start condition detection
Stop condition detection
Falling edge
detection
UART2
transmission/NACK
interrupt request
UART2 reception/ACK
interrupt request
DMAi request
9th pulse
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
L-synchronous
output enabling bit
Bus collision/start, stop
condition detection
interrupt request
Bus collision
detection
Noize
Filter
I/0
Noize
Filter
P70/TXD2/SDA
P71/RXD2/SCL
CLK
control
Internal clock
UART2
Serector
UART2
I/0
Timer
P72/CLK2
Data register
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UART2
R
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1 and
IICM2=0
IICM=0
IICM=1
IICM=0
S
R
Q
Bus
busy
IICM=1
IICM=0
ALS
R
S
SWC
Falling edge of 9th pulse
IICM=1 and
IICM2=0
IICM=0 or IICM2=1
IICM=0 or
IICM2=1
SWC2
SDHI
To DMAi
Selector
Transmission register
UART2
Noize
Filter
Figure 1.20.2. Functional block diagram for I2C mode
Figure 1.20.2 is a block diagram of the IIC bus interface.
To explain the control bit of the IIC bus interface, UART2 is used as an example.
UART2 Special Mode Register (Address 033716)
Bit 0 is the IIC mode select bit. When set to “1”, ports P70, P71 and P72 operate respectively as the
SDA2 data transmission-reception pin, SCL2 clock I/O pin and port P72. A delay circuit is added to
SDA2 transmission output, therefore after SCL2 is sufficiently L level, SDA2 output changes. Port P71
(SCL2) is designed to read pin level regardless of the content of the port direction register. SDA2
transmission output is initially set to port P70 in this mode. Furthermore, interrupt factors for the bus
collision detection interrupt, UART2 transmission interrupt and UART2 reception interrupt change
respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and
acknowledge detection interrupt.