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參數(shù)資料
| 型號： | M34524EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 20/66頁 |
| 文件大?。?/td> | 1936K |
| 代理商： | M34524EDFP |
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Rev.1.04
Aug 23, 2007
Page 27 of 146
REJ03B0188-0104
4559 Group
EXTERNAL INTERRUPTS
The 4559 Group has the external 0 interrupt. An external
interrupt request occurs when a valid waveform is input to an
interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Fig 28. External interrupt circuit structure
Table 14 External interrupt activated conditions
Name
Input pin
Activated condition
Valid waveform
selection bit
External 0 interrupt
D5/INT
When the next waveform is input to D5/INT pin
Falling waveform (
“H”
→ “L”)
Rising waveform (
“L”
→ “H”)
Both rising and falling waveforms
I11
I12
Key-on wakeup input
SNZI0 instruction
(Note 1)
K21
0
1
Edge detection circuit
Level detection circuit
D5/INT
I13
I12
Falling
0
1
Rising
K20
I11
0
1
One-sided edge
detection circuit
Both edges
detection circuit
Skip
EXF0
External 0
interrupt
Timer 1 count start
synchronization
circuit input
(Note 2)
(Note 3)
Note 1:
This symbol represents a parasitic diode on the port.
2: When
I12= 0(X=0 or 1) is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
(Note 1)
or
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