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參數(shù)資料
| 型號(hào)： | M34524EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 22/66頁 |
| 文件大?。?/td> | 1936K |
| 代理商： | M34524EDFP |
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Rev.1.04
Aug 23, 2007
Page 29 of 146
REJ03B0188-0104
4559 Group
(3) Notes on interrupts
(1) Bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of
register I1 in software, be careful about the following notes.
Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 29.) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 29.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
29.).
Fig 29. External 0 interrupt program example-1
(2) Bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the power
down mode is selected and the input of INT pin is disabled,
be careful about the following notes.
When the INT pin input is disabled (register I13 = “0”), set the
key-on wakeup of INT pin to be invalid (register K20 = “0”)
before system enters to power down mode. (refer to (1) in
Fig 30. External 0 interrupt program example-2
(3) Bit 2 of register I1
When the interrupt valid waveform of the INT pin is
changed with the bit 2 of register I1 in software, be careful
about the following notes.
Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 31.) and then, change the bit 2 of register I1 is
changed.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 31.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
31.).
Fig 31. External 0 interrupt program example-3
LA 4
; (
×××02)
TV1A
; The SNZ0 instruction is valid ...... (1)
LA 8
; (1
×××2)
TI1A
; Control of INT pin input is changed
NOP
...................................................... (2)
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...................................................... (3)
×: these bits are not used here.
LA 0
; (
×××02)
TK2A
; INT0 key-on wakeup disabled .....(1)
DI
EPOF
POF2
; RAM back-up
×: these bits are not used here.
LA 4
; (
×××02)
TV1A
; The SNZ0 instruction is valid ......(1)
LA 12
; (
×1××2)
TI1A
; Interrupt valid waveform is changed
NOP
.......................................................(2)
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
.......................................................(3)
×: these bits are not used here.
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