參數(shù)資料
型號(hào)： M34524EDFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù)： 48/66頁
文件大?。?/td> 1936K
代理商： M34524EDFP
Rev.1.04
Aug 23, 2007
Page 53 of 146
REJ03B0188-0104
4559 Group
VOLTAGE DROP DETECTION CIRCUIT (WITH SKIP
JUDGMENT)
The built-in voltage drop detection circuit is used to set the
voltage drop detection circuit flag (VDF) or to perform system
reset.
Fig 53. Voltage drop detection reset circuit
(1) Operating state of voltage drop detection circuit
The voltage drop detection circuit becomes valid by inputting
“H” to the VDCE pin and it becomes invalid by inputting “L.”
When not executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit become invalid in
power down state (RAM back-up, clock operating mode). As for
this, the voltage drop detection circuit becomes valid at returning
from power down, again.
When executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit becomes valid in
power down state (RAM back-up, clock operating mode).
The state of executing SVDE instruction can be cleared by
system reset.
Note. “O” indicates valid, “×” indicates invalid.
(Note 1)
VDCE
(Note 2)
VRST-/VRST+
+
Voltage drop
detection circuit
VSKIP
+
Flag occurrence
Reset occurrence
VDF
VDD
Voltage drop
detection circuit
reset signal
S
R
Q
S
R
Q
SVDE instruction
Internal reset signal
EPOF instruction + POF instruction
EPOF instruction + POF2 instruction
Key-on wakeup signal
Internal reset signal
Voltage drop
detection circuit flag
Skip judgement
(SNZVD
instruction)
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Timer 3 underflow signal
Table 22 Operating state of voltage drop detection circuit
VDCE pin
SVDE instruction
at CPU operating
at power down
“L”
No execute
×
Execute
×
“H”
No execute
O
×
Execute
O
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