參數(shù)資料
型號： M34552G8FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 41/143頁
文件大?。?/td> 0K
代理商： M34552G8FP
14: CLOCKING
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-123
SPECIFICATION (X23A-A-001-12)
Bandwidth during display period
= MIN (bandwidth during non display period, B/C/D)
where B = number of MCLKs left available for CPU access after every 16 pixels drawn
= (f(MCLK)/f(PCLK) * 16 - Total MCLK for Display refresh), units in MCLKs 16 pixels
where C = number of MCLKs required to service 1 CPU access (2 bytes of data)
= 4, units in MCLKs/2 bytes
where D = time to draw 16 pixels
= 16 / f(PCLK), units in 16 pixels
The minimum function limits the bandwidth to the bandwidth available during non display period
should the display fetches constitute a small percentage of the overall memory activity.
For 16 bpp single panel/CRT/dual panel with half frame buffer disable, the number of MCLKs
required to fetch 16 pixels when PCLK = MCLK exceeds 16. In this case, the display fetch does not
allow any CPU access during the display period. CPU access can only be achieved during non dis-
play periods.
Average Bandwidth
All displays have a horizontal non display period, and a vertical non display period. The formula for
calculating the percentage of non display period is as follows
Percentage of non display period = (HTOT * VTOT - WIDTH * HEIGHT)/(HTOT * VTOT)
Percentage of non display period for CRT = (800*525 - 640*480)/(800*525) = 26.6%
Percentage of non display period for single panel = (680*482 - 640*480)/680*482) = 6.2%
Percentage of non display period for dual panel = (680*242 - 640*240)/680*242) = 6.6%
Average Bandwidth =
Percentage of non display period * Bandwidth during non display period +
(1- Percentage of non display period) * Bandwidth during display period
Table 14-5 Total # MCLKs Taken for Display Refresh
Display
MCLKs for Display Refresh
1 bpp
2 bpp
4 bpp
8 bpp
16 bpp
Single Panel.
CRT.
Dual Monochrome/Color Panel with Half Frame Buffer Disabled.
Simultaneous CRT + Single Panel.
Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer
Disabled.
4
5
7
11
19
Dual Monochrome Panel with Half Frame Buffer Enabled.
Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable.
11
12
14
18
26
Dual Color Panel with Half Frame Buffer Enabled.
15
16
18
22
30
相關(guān)PDF資料
PDF描述
M34552M8H-XXXFP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP48
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M34556G8HFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
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M34556M8H-XXXFP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34552G8HFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34552M4H-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34552M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34552M8H-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34552M8-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
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