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參數(shù)資料
| 型號： | M36L0R7050T0ZAQF |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package |
| 中文描述： | 128兆位（多銀行，多層次，突發(fā)）閃存32兆位（200萬× 16）移動存儲芯片，1.8V電源多芯片封裝 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 406K |
| 代理商： | M36L0R7050T0ZAQF |
M36L0R7050T0, M36L0R7050B0
6/18
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
and
Table 1., Signal
Names
, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22).
Addresses
are common inputs for the Flash Memory and the
PSRAM components. The other lines (A21-A22)
are inputs for the Flash Memory components only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the PSRAM.
The Flash memory component is accessed
through the Chip Enable signal (E
F
) and through
the Write Enable (W
F
) signal, while the PSRAM is
accessed through two Chip Enable signals (E1
P
and E2
P
) and the Write Enable signal (W
P
).
Data Input/Output (DQ0-DQ15).
In the Flash
memory the Data I/O outputs the data stored at the
selected address during a Bus Read operation or
inputs a command or the data to be programmed
during a Write Bus operation.
In the PSRAM the Lower Byte Data Inputs/Out-
puts, DQ0-DQ7, carry the data to or from the lower
part of the selected address during a Write or
Read operation, when Lower Byte Enable (LB
P
) is
driven Low.
The Upper Byte Data Inputs/Outputs, DQ8-DQ15,
carry the data to or from the upper part of the se-
lected address during a Write or Read operation,
when Upper Byte Enable (UB
P
) is driven Low.
Flash Chip Enable (E
F
).
The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is Low, V
IL
, and
Reset is High, V
IH
, the device
is in active mode. When Chip Enable is at V
IH
the
Flash memory is deselected, the outputs are high
impedance and the power consumption is reduced
to the standby level.
Flash Output Enable (G
F
).
The Output Enable
input controls data output during Flash memory
Bus Read operations.
Flash Write Enable (
W
F
).
The
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
F
).
Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
IL
,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
IH
, Lock-Down is
disabled and the Locked-Down blocks can be
A0-A20
Write
Enable
locked or unlocked. (See the Lock Status Table in
the M30L0R7000T0 datasheet).
Flash Reset (RP
F
).
The Reset input provides a
hardware reset of the memory. When Reset is at
V
IL
, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current I
DD2
. Refer to
Table 7., Flash Memory DC Characteristics - Cur-
rents
, for the value of I
DD2
. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at V
IH
, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to
Table 8., Flash Memory DC Characteris-
tics - Voltages
).
Flash Latch Enable (L
F
).
Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, V
IL
,
and it is inhibited when Latch Enable is High, V
IH
.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (K
F
).
The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V
IL
. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAIT
F
).
WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at V
IH
or Flash Reset is at V
IL
. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAIT
F
signal is not gated
by Output Enable.
PSRAM Chip Enable (E1
P
).
When
(Low), the Chip Enable, E1
P
, activates the memo-
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
It is not allowed to set E
F
at V
IL,
E1
P
at V
IL
and E2
P
at V
IH
at the same time.
PSRAM Chip Enable (E2
P
).
The Chip Enable,
E2
P
, puts the device in Power-down mode (Deep
Power-Down or a Partial Power-Down mode)
when it is driven Low. Deep Power-down mode is
the lowest power mode.
asserted
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M36L0R7050T0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package |
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