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參數(shù)資料
| 型號： | M36LLR876B0E |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package |
| 中文描述： | 256 128兆位（多銀行，多層次，突發(fā)）64兆位閃存（突發(fā)）移動存儲芯片，1.8V電源，多芯片封裝 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 427K |
| 代理商： | M36LLR876B0E |
5/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 2. Logic Diagram
Table 1. Signal Names
Note: 1. A22 is an Address Input for the two Flash memories only.
A23 is for the 256Mb Flash memory component only.
AI10908b
24
A0-A23
DQ0-DQ15
M36LLR8760T1
M36LLR8760D1
M36LLR8760M1
M36LLR8760B1
G
F1
E
F2
16
W
F
RP
F
WP
F
E
P
G
P
W
P
CR
P
UB
P
LB
P
VSS
V
PPF
V
CCP
WAIT
L
K
V
DDQF
E
F1
V
DDF2
V
DDF1
G
F2
A0-A23
(1)
Address Inputs
DQ0-DQ15 Common Data Input/Output
L
Common Flash and PSRAM Latch
Enable Input
K
Common Flash and PSRAM Burst Clock
WAIT
Wait Data in Burst Mode for both Flash
memories and PSRAM
V
DDF1
Flash 1 Power Supply
V
DDF2
Flash 2 Power Supply
V
DDQF
Common Flash Supply for I/O Buffers
V
PPF
Common Flash Optional Supply Voltage
for Fast Program & Erase
V
SS
Common, Ground
V
CCP
PSRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory Signals
E
F1
Flash 1 Chip Enable Input
G
F1
Flash 1 Output Enable Input
E
F2
Flash 2 Chip Enable Input
G
F2
Flash 2 Output Enable Input
W
F
Common Flash Memory Write Enable
Input
RP
F
Common Flash Memory Reset input
WP
F
Common Flash Memory Write Protect
Input
PSRAM Signals
E
P
Chip Enable Input
G
P
Output Enable Input
W
P
Write Enable Input
CR
P
Configuration Register Enable Input
UB
P
Upper Byte Enable Input
LB
P
Lower Byte Enable Input
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