參數(shù)資料
型號(hào)： M36W0R6030T0ZAQ
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
中文描述： 64兆位（4Mb的x16插槽，多銀行，突發(fā)）閃存和8兆位（512KB的× 16）的SRAM，多芯片封裝
文件頁(yè)數(shù)： 11/26頁(yè)
文件大?。?/td> 168K
代理商： M36W0R6030T0ZAQ
11/26
M36W0R6030T0, M36W0R6030B0
SRAM OPERATIONS
There are five standard operations that control the
device. These are Read, Write, Standby/Power-
down, Data Retention and Output Disable.
Read.
Read operations are used to output the
contents of the SRAM Array.
The device is in Byte Read mode whenever Write
Enable, W
S
, is at V
IH
, Output Enable, G
S
, is at V
IL
,
Chip Enable, E1
S
, is at V
IL
, Chip Enable, E2
S
, is at
V
IH
, and UB
S
or LB
S
is at V
IL
.
The device is in Word Read mode whenever Write
Enable, W
S
, is at V
IH
, Output Enable, G
S
, is at V
IL
,
Byte Enable inputs UB
S
and LB
S
are both at V
IL
and the two Chip Enable inputs, E1
S
, and E2
S
are
Don’t Care.
The Read and Standby AC Waveforms are shown
in Figures
9
and
10
, respectively and the parame-
ters are given in
Table 9., Read AC Characteris-
tics
.
Write.
Write operations are used to write data to
the SRAM. The device is in Write mode whenever
W
S
, E1
S
and UB
S
and/or LB
S
are at V
IL
, and E2
S
is at V
IH
. All these signals must be asserted to ini-
tiate a Write cycle. The data is latched on the fall-
ing edge of E1
S
, the rising edge of E2
S
, the falling
edge of W
S
, or the falling edge of UB
S
and/or LB
S
,
whichever occurs last. The Write cycle will termi-
nate on the rising edge of E1
S
, the rising edge of
W
S
, the rising edge of UB
S
and/or LB
S
, or the fall-
ing edge of E2
S
, whichever occurs first. The tim-
ings are referenced to the signal that terminates
the Write cycle.
The outputs are disabled during Write cycles
(whenever E1
S
, at V
IL
, E2
S
at V
IH
, and W
S
at V
IL
).
The Write AC Waveforms are shown in Figures
11
,
12
,
13
and
14
, while
Table 10.
gives the Write
AC Characteristics.
Standby/Power-Down.
The device automatically
enters the Standby/Power-Down mode when
DQ0-DQ15 are not toggling, reducing the power
consumption to the Standby level, I
SB
.
The device is also in Standby/Power-Down mode
whenever E1
S
is at V
IH
, E2
S
is at V
IL
or both UB
S
and LB
S
are at V
IH
. The outputs then become high
impedance.
The Standby AC Waveforms are shown in
Figure
10.
See
Table 9., Read AC Characteristics
, for
timings.
Data Retention.
The data retention mode is en-
tered t
CDR
after de-asserting E1
S
,
E2
S
or UB
S
and
LB
S
. The data retention performance as V
DD
goes
down to V
DR
is described in
Table 11.
, Figures
15
and
16
,
SRAM Low V
DD
Data Retention AC Wave-
forms, E1
S
or UB
S
/ LB
S
Controlled
and
SRAM
Low V
DD
Data Retention AC Waveforms, E2
S
Controlled
, respectively.
Output Disable.
The device is in the Output Dis-
able mode whenever G
S
, is at V
IH
. In this mode,
DQ0-DQ15 are high impedance.
相關(guān)PDF資料
PDF描述
M36W0R6030T0ZAQE 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
M36W0R6030T0ZAQF 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
M36W0R6030T0ZAQT 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
M36W0R6050B1 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package
M36W0R6050B1ZAQE 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M36W0R6030T0ZAQE 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
M36W0R6030T0ZAQF 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
M36W0R6030T0ZAQT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
M36W0R604040B0ZAQE 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 16 Mbit (1 Mb 】16) PSRAM, multi-chip package
M36W0R604040B0ZAQF 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 16 Mbit (1 Mb 】16) PSRAM, multi-chip package
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*