參數(shù)資料
型號: M36W108T100ZM1T
廠商: 意法半導(dǎo)體
英文描述: Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述: 8兆1兆× 8,啟動塊閃存和1兆位128KB的x8 SRAM的低電壓多媒體存儲產(chǎn)品
文件頁數(shù): 4/35頁
文件大?。?/td> 247K
代理商: M36W108T100ZM1T
M36W108T, M36W108B
4/35
Reset Input (RP).
The Reset input provides
hardware reset of the Flash chip. Reset of the
Flash memory is achieved by pulling RP to V
IL
for
at least t
PLPX
. When the reset pulse is given, if the
Flash memory is in Read or Standby modes, it will
be available for new operations in t
PHEL
after the
rising edge of RP.
If the Flash memory is in Erase or Program mode
the reset will take t
PLYH
during which the Ready/
Busy (RB) signal will be held at V
IL
. The end of the
Flash memory reset will be indicated by the rising
edge of RB. A hardware reset during an Erase or
Program operation will corrupt the data being pro-
grammed or the block(s) being erased. See Table
17 and Figure 9.
Ready/Busy Output (RB).
Ready/Busy
open-drain output of the Flash chip. It gives the in-
ternal state of the Program/Erase Controller (P/
E.C.) of the Flash device. When RB is Low, the
Flash device is busy with a Program or Erase op-
eration and it will not accept any additional pro-
gram or erase instructions except the Erase
Suspend instruction. When RB is High, the Flash
device is ready for any Read, Program or Erase
operation. The RB will also be High when the
Flash memory is put in Erase Suspend or Standby
modes.
is an
V
CCF
Supply Voltage.
Flash memory power sup-
ply for all operations (Read, Program and Erase).
V
CCS
Supply Voltage.
SRAM power supply for
all operations (Read, Program).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
POWER SUPPLY
Power Up.
The Flash memory Command Inter-
face is reset on power up to Read Array. Either
Flash Chip Enable (EF) or Write Enable (W) inputs
must be tied to V
IH
during Power Up to allow max-
imum security and the possibility to write a com-
mand on the first rising edge of EF and W. Any
write cycle initiation is blocked when V
CCF
is below
V
LKO
.
Supply Rails.
Normal precautions must be taken
for supply voltage decoupling; each device in a
system should have the V
CCF
, V
CCS
rails decou-
pled with a 0.1μF capacitor close to the V
CCF
,
V
CCS
and V
SS
pins. The PCB trace widths should
be sufficient to carry the V
CCF
and V
CCS
program
currents and the V
CCF
erase current required.
Table 3. Main Operation Modes
(1)
Note: 1. X = V
IL
or V
IH
.
Operation Mode
EF
E1S
E2S
G
W
RP
DQ0-DQ7
Flash Chip Read
V
IL
V
IH
X
V
IL
V
IH
V
IH
Data Output
V
IL
X
V
IL
V
IL
V
IH
V
IH
Data Output
SRAM Chip Read
V
IH
V
IL
V
IH
V
IL
V
IH
X
Data Output
Flash Chip Write
V
IL
V
IH
X
V
IH
V
IL
V
IH
Data Input
V
IL
X
V
IL
V
IH
V
IL
V
IH
Data Input
SRAM Chip Write
V
IH
V
IL
V
IH
X
V
IL
X
Data Input
Flash Chip Output Disable
X
V
IH
X
V
IH
V
IH
X
Hi-Z
X
X
V
IL
V
IH
V
IH
X
Hi-Z
SRAM Chip Output Disable
V
IH
V
IL
V
IH
V
IH
V
IH
X
Hi-Z
Flash Chip Stand-by
V
IH
X
X
X
X
V
IH
Hi-Z
Flash Chip Reset
X
V
IH
X
X
X
V
IL
Hi-Z
X
X
V
IL
X
X
V
IL
Hi-Z
SRAM Chip Stand-by
X
V
IH
X
X
X
V
IL
Hi-Z
X
X
V
IL
X
X
V
IL
Hi-Z
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