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參數(shù)資料
| 型號(hào)： | M36W108T120ZM1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Jacket Color:Blue; Leaded Process Compatible:Yes; Voltage Nom.:30V RoHS Compliant: Yes |
| 中文描述： | 8兆1兆× 8，啟動(dòng)塊閃存和1兆位128KB的x8 SRAM的低電壓多媒體存儲(chǔ)產(chǎn)品 |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 247K |
| 代理商： | M36W108T120ZM1T |
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M36W108T, M36W108B
14/35
SRAM COMPONENT
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 13).
Read.
Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (W) is at V
IH
with
Output Enable (G) at V
IL
, and both Chip Enables
(E1S and E2S) are asserted.
Valid data will be available at the eight output pins
within t
AVQV
after the last stable address, provid-
ing G is Low, E1S is Low and E2S is High. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limit-
ing parameter (t
E1LQV
, t
E2HQV
, or t
GLQV
) rather
than the address. Data out may be indeterminate
at t
E1LQX
, t
E2HQX
and t
GLQX
, but data lines will al-
ways be valid at t
AVQV
(see Table 21, Figure 14,
Figure 15).
Write.
Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the W and E1S pins are at V
IL
, with E2S at V
IH
. Ei-
ther the Chip Enable inputs (E1S and E2S) or the
Write Enable input (W) must be de-asserted dur-
ing address transitions for subsequent write cy-
cles. Write begins with the concurrence of both
Chip Enables being active with W at V
IL
. A Write
begins at the latest transition among E1S going to
V
IL
, E2S going to V
IH
and W going to V
IL
. There-
fore, address setup time is referenced to Write En-
able and both Chip Enables as t
AVWL
, t
AVE1L
and
t
AVE2H
respectively, and is determined by the latter
occurring edge. The Write cycle can be terminated
by the rising edge of E1S, the rising edge of W or
the falling edge of E2S, whichever occurs first.
If the Output is enabled (E1S=V
IL
, E2S=V
IH
and
G=V
IL
), then W will return the outputs to high im-
pedance within t
WLQZ
of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
DVWH
before
the rising edge of Write Enable, or for t
DVE1H
be-
fore the rising edge of E1S or for t
DVE2L
before the
falling edge of E2S, whichever occurs first, and re-
main valid for t
WHDX
, t
E1HDX
or t
E2LDX
(see Table
22, Figures 17, 18, 19).
Output Disable.
The data outputs are high im-
pedance when the Output Enable (G) is at V
IH
with
Write Enable (W) at V
IH
.
Power-Down.
The SRAM chip has a Chip Enable
power-down feature which invokes an automatic
standby mode (see Table 21, Figure 16) whenever
either Chip Enable is de-asserted (E1S=V
IH
or
E2S=V
IL
).
Data Retention
The SRAM data retention performances as V
CCS
go down to V
DR
are described in Table 23 and Fig-
ures 22, 23. In E1S controlled data retention
mode, minimum standby current mode is entered
when E1S
≥
V
CCS
– 0.2V and E2S
≤
0.2V or
E2S
≥
V
CCS
– 0.2V. In E2S controlled data reten-
tion mode, minimum standby current mode is en-
tered when E2S
≤
0.2V.
Table 13. SRAM User Bus Operations
(1)
Note: 1. X = V
IL
or V
IH
.
Operation
E1S
E2S
W
G
DQ0-DQ7
Power
Read
V
IL
V
IH
V
IH
V
IL
Data Output
Active
Write
V
IL
V
IH
V
IL
X
Data Input
Active
Output Disable
V
IL
V
IH
V
IH
V
IH
Hi-Z
Active
Power Down
V
IH
X
X
X
Hi-Z
Stand-by TTL
X
V
IL
X
X
Hi-Z
Stand-by TTL/CMOS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36W108T120ZM5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product |
| M36W108T120ZM6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product |
| M36W108T120ZN1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product |
| M36W108T120ZN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product |
| M36W108T120ZN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product |
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