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參數(shù)資料
| 型號(hào)： | M37274EFSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件頁數(shù)： | 84/147頁 |
| 文件大小： | 2042K |
| 代理商： | M37274EFSP |
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41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
Fig. 36. Vsep Generating Timing (method 2)
Composite
sync signal
Timing
signal
Vsep signal
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Measure “L” period
(3) Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
Horizontal synchronous signal (Hsep)
A one-shot horizontal synchronous signal Hsep is generated at
the falling edge of the composite sync signal.
Vertical synchronous signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 7 of the sync slice register
(address 00E316).
Method 1
The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
Method 2
The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync
signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists,
a Vsep signal is generated in synchronization with
the rising of the timing signal (refer to Figure 36).
Figure 36 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 38, when the A level matches the B level, this bit is
“0.” In the case of a mismatch, the bit is “1.”
For the pins RVCO and the HLF, connect a resistor and a capacitor
as shown in Figure 31. Make the length of wiring which is connected
to these pins as short as possible so that a leakage current may not
be generated.
Note: It takes a few tens of milliseconds until the reference clock
becomes stable after the data slicer and the timing signal
generating circuit are started. In this period, various timing
signals, Hsep signals and Vsep signals become unstable. For
this reason, take stabilization time into consideration when
programming.
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