參數(shù)資料
型號： M37281EKSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 65/172頁
文件大?。?/td> 1319K
代理商： M37281EKSP
Rev.1.01 2003.07.16 page 65 of 170
M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
Fig. 8.10.12 Sync Pulse Counter Register
8.10.13 Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal V
sep
as a count source.
The count value in a certain time (T time) generated by f(X
IN
)/2
13
or
f(X
IN
)/2
13
is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds
“
1F
16
,
”
“
1F
16
”
is stored into the latch.
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
The latch value can be obtained by reading out the sync pulse counter
register (address 00E9
16
). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 0208
16
).
Figure 8.10.12 shows the structure of the sync pulse counter and
Figure 8.10.13 shows the synchronous signal counter block diagram.
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E9
16
]
R W
Sync Pulse Counter Register
0
to
4
Indeterminate
R
—
6, 7
0
R
—
Count value (HC0 to HC4)
5
0
R W
Count source (HC5)
0: H
SYNC
signal
1: Composite sync signal
B
After reset
Functions
Name
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are
“
0.
”
Reset
5-bit counter
Latch (5 bits)
f(X
IN
)/2
13
Composite
sync signal
H
SYNC
signal
Counter
Sync pulse
counter register
Data bus
Selection gate : connected to black
side when reset.
b5
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M37281MKH-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
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