參數(shù)資料
型號(hào)： M37512F8HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 72/89頁(yè)
文件大?。?/td> 877K
代理商： M37512F8HP
Feb 18, 2005
page 72 of 85
REJ03B0122-0101
7512 Group
Electrical characteristics for Flash ROM E/W Cycles
Table 18 Characteristics (Note 1) for 100 E/W cycle products
(VCC = 2.5V±2%, Ta = 0 to 60 oC, unless otherwise noted)
Erase/Write cycle (Note 3)
Byte write time
Block erase time
2Kbyte block
8Kbyte block
16Kbyte block
Time delay from Suspend Request until Erase Suspend
Data retention time (Note 5)
Limits
Parameter
Min.
Typ.
(Note 2)
Max.
Symbol
VCC=2.5V, Ta=25°C
Condition
—
td(SR–ES)
—
100 (Note 4)
20
75
0.2
0.4
0.7
600
9
8
cycle
s
ms
year
Erase/Write cycle (Note 3, 8, 9)
Byte write time
Block erase time (2Kbyte block)
Time delay from Suspend Request until Erase Suspend
Limits
Parameter
Min.
Typ.
(Note 2)
Max.
Symbol
Unit
VCC=2.5V, Ta=25°C
Condition
—
td(SR–ES)
1000 (Note 4)
100
0.3
8
cycle
s
ms
Table 19 Characteristics (Note 6) for 1000 E/W cycle products [Block A and Block B (Note 7)]
(VCC = 2.5V±2%, Ta = –20 to 85 oC, unless otherwise noted)
Notes 1: Specified for all blocks.
2: VCC=2.5V; Ta=25°C.
3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total number of distinct byte addresses -
for every block erase. Performing multiple writes to the same address before an erase operation is prohibited.
4: Maximum number of E/W cycles for which operation is guaranteed.
5: At Ta=55°C condition
6: Specified for Block A and Block B E/W cycles > 100
7: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different byte addresses (only one time each)
as possible. It is important to track the total number of block erases.
8: Should erase error occur during block erase, attempt to execute clear status register command, then block erase command at least three times un-
til erase error disappears.
9: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Erase suspend request bit
(Interrupt request)
Erase suspend flag
td(SR-ES)
Fig. 77 The transition of the timing of the erase / erase suspend
Unit
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