- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45035 > M37546G4-XXXHP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36 PDF資料下載
參數(shù)資料
| 型號(hào)： | M37546G4-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, PLASTIC, WQFN-36 |
| 文件頁(yè)數(shù)： | 22/103頁(yè) |
| 文件大小： | 1156K |
| 代理商： | M37546G4-XXXHP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)
REJ03B0160-0122 Rev.1.22 Mar 13, 2009
page 25 of 100
7546 Group
Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source (ex-
ternal interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance con-
ditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of the interrupt request bit for an unaccepted interrupt
remains the same and acceptance is determined at the next
interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Fig. 22 shows the time up to execution in the interrupt processing
routine, and Fig. 23 shows the interrupt sequence.
Fig. 24 shows the timing of interrupt request generation, interrupt
request bit, and interrupt request acceptance.
Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
(1) Once the currently executing instruction is completed, an in-
terrupt request is accepted.
(2) The contents of the program counters and the processor sta-
tus register at this point are pushed onto the stack area in
order from 1 to 3.
1.High-order bits of program counter (PCH)
2.Low-order bits of program counter (PCL)
3.Processor status register (PS)
(3) Concurrently with the push operation, the jump address of the
corresponding interrupt (the start address of the interrupt pro-
cessing routine) is transferred from the interrupt vector to the
program counter.
(4) The interrupt request bit for the corresponding interrupt is set
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the reg-
isters pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each inter-
rupt to execute the interrupt processing routine.
Fig. 22 Time up to execution in interrupt routine
Main routine
Interrupt handling
routine
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
7 cycles
0 to 16* cycles
7 to 23 cycles
* When executing DIV instruction
Stack push
Vector fetch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37546G2GP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| M37546G2HP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36 |
| M37546G4-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37546G4-XXXGP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| M37547G2-XXXFP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37546G4-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37547G2FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37547G2FP#U0 | 功能描述:MCU 2/5V 8KB 36-SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| M37547G2-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37547G4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。