參數(shù)資料
型號(hào)： M37546G4-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36
封裝： 6 X 6 MM, 0.50 MM PITCH, PLASTIC, WQFN-36
文件頁(yè)數(shù)： 96/103頁(yè)
文件大?。?/td> 1156K
代理商： M37546G4-XXXHP
REJ03B0160-0122 Rev.1.22 Mar 13, 2009
page 92 of 100
7546 Group
APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a re-
set.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations. Initialize these flags
at beginning of the program.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Fig.2 Stack memory contents after PHP instruction execution
2. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the
SED instruction. After executing the ADC or SBC instruction, ex-
ecute another instruction before executing the SEC, CLC, or CLD
instruction.
(S)
(S)+1
Stored PS
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To de-
termine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calcula-
tion.
3. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
4. Multiplication and Division Instructions
(1) The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
(2) The execution of these instructions does not change the con-
tents of the processor status register.
5. Read-modify-write instruction
Do not execute a read-modify-write instruction to the read invalid
address (SFR).
The read-modify-write instruction operates in the following se-
quence: read one-byte of data from memory, modify the data,
write the data back to original memory. The following instructions
are classified as the read-modify-write instructions in the 740
Family.
(1) Bit management instructions: CLB, SEB
(2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF
(3) Add and subtract instructions: DEC, INC
(4) Logical operation instructions (1’s complement): COM
Add and subtract/logical operation instructions (ADC, SBC, AND,
EOR, and ORA) when T flag = “1” operate in the way as the read-
modify-write instruction. Do not execute the read invalid SFR.
<Reason>
When the read-modify-write instruction is executed to read invalid
SFR, the instruction may cause the following consequence: the in-
struction reads unspecified data from the area due to the read
invalid condition. Then the instruction modifies this unspecified
data and writes the data to the area. The result will be random
data written to the area or some unexpected event.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3 Instructions for decimal calculations
Reset
↓
Initializing of flags
↓
Main program
Fig. 1 Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS), ex-
ecute the PHP instruction once then read the contents of (S+1). If
necessary, execute the PLP instruction to return the PS to its origi-
nal status.
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