CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual
2-16
2.2 Bus interface unit (BIU)
16-bit data access starting from an odd-numbered address
s When the external data bus width = 16 bits (BYTE = VSS level)
(a) When accessing 16-bit data starting from an even-numbered address
< At reading >
< At writing >
Address
φ1
External address bus
( A0–A23 )
External data bus
( D0–D7 )
External data bus
( D8–D15 )
RD
BLW
BHW
H
Address
WD
(even)
WD
(odd)
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15)
RD
BLW
BHW
H
Address
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15)
RD
BLW
BHW
Address + 1
16-bit data access starting from odd-numbered address
8-bit data access to
odd-numbered
address
WD
(odd)
Address
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15)
RD
BLW
BHW
H
Address + 1
8-bit data access to
odd-numbered
address
WD
(even)
Address
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15 )
RD
BLW
BHW
H
Address + 2
< At reading >
< At writing >
WD (even)
WD (odd)
Address
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15)
RD
BLW
BHW
H
Address + 2
WD (even)
WD (odd)
(d) When accessing 32-bit data starting from odd-numbered address
< At reading >
< At writing >
Address
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15)
RD
BLW
BHW
H
Address + 1
Address + 3
Address
Address + 1
Address + 3
WD (odd)
φ1
External address bus
(A0–A23)
External data bus
(D0–D7)
External data bus
(D8–D15)
RD
BLW
BHW
H
WD (even)
WD (odd)
WD (even)
< At reading >
< At writing >
Invalid
RD
(odd)
RD
(even)
RD
(odd)
RD
(even)
Invalid
RD: Data to be read, WD: Data to be written
Invalid: Invalid data. At reading, this data is not taken into a data buffer.
Note: The above waveforms apply when bus cycle = 1
φ + 1φ at normal access.
For any of the bus cycle, recovery cycle, and burst ROM access, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
RD
(even)
RD
(odd)
(b) When accessing 16-bit data starting from an odd-numbered address
or accessing 8-bit data
H
8-bit data access to
even-numbered
address
(c) When accessing 32-bit data starting from an even-numbered address
RD
(even)
RD
(odd)
RD
(even)
RD
(even)
RD
(odd)
RD
(odd)
8-bit data access to
even-numbered
address
Fig. 2.2.5 Operating waveform examples at reading from or writing to external area (1)