7902 Group User’s Manual
APPENDIX
21-42
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Serial I/O pin control register (Address AC16)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
CTS0/RTS0 separate select bit
(Note)
CTS1/RTS1 separate select bit
(Note)
TxD0/P83 switch bit
TxD1/P87 switch bit
The value is “0” at reading.
0 : CTS0/RTS0 are used together.
1 : CTS0/RTS0 are separated.
0 : Functions as TxD1.
1 : Functions as P87.
RW
—
Bit name
Bit
Function
At reset
R/W
0 : CTS1/RTS1 are used together.
1 : CTS1/RTS1 are separated.
0 : Functions as TxD0.
1 : Functions as P83.
0
1
0
Clock control register (Address BC16)
Bit name
Bit
Function
At reset
R/W
Fix this bit to “1.”
PLL circuit operation enable bit
(Note 1)
PLL multiplication ratio select bits
(Note 2)
Fix this bit to “0.”
System clock select bit
(Note 3)
Peripheral device’s clock select bit 0
Peripheral device’s clock select bit 1
b7 b6 b5 b4 b3 b2 b1 b0
0 : PLL frequency muliplier is inactive, and pin VCONT
is invalid. (Floating)
1 : PLL frequency muliplier is active, and pin VCONT is
valid.
0 0 : Do not select.
0 1 : Double
1 0 : Triple
1 1 : Quadruple
b3 b2
See Table 5.2.2.
0 : fXIN
1 : fPLL
01
RW
Reference
12-17
Reference
5-6
5-7
Notes 1: Clear this bit to “0” if the PLL frequency multiplier need not to be active.
In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regard-
less of the contents of this bit.
2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5). Then, set
bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.)
3: Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL circuit
operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”)
In order to set the system clock select bit to “1” after reset, it is necessary to wait 2 ms after the stabilization of f(XIN).
Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416 and 3C16) is “0.”