65
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
The FERi, PERi, and SUMi flags are cleared to “0” when reading the
low-order byte of the receive buffer register or when writing “0” to the
REi flag.
The OERi flag is cleared to “0” when writing “0” to the REi flag.
Interrupt request at completion of reception
When the RIk flag changes from “0” to “1”, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to “1”.
The timing when this interrupt request bit is to be set to “1” can be
selected from the following:
Each reception
When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART re-
ceive interrupt mode select bit) is cleared to “0”, the interrupt request
bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt
request bit is set to “1” only when an error occurs. (In the clock asyn-
chronous serial communication, when an overrun error, framing er-
ror, or parity error occurs, the interrupt request bit is set to “1”.)
Sleep mode
The sleep mode is used to communicate only between certain micro-
computers when multiple microcomputers are connected through
serial I/O.
The microcomputer enters the sleep mode when bit 7 of UARTi
transmit/receive mode register is set to “1”.
The operation of the sleep mode for an 8-bit asynchronous commu-
nication is described below.
When sleep mode is selected, the contents of the receive register is
not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn-
chronous communication and bit 8 if 9-bit asynchronous communi-
cation) of the received data is “0”. Also the RIi, OERi, FERi, PERi,
and the SUMi flags are unchanged. Therefore, the interrupt request
bit of the UARTi receive interrupt control register is also unchanged.
Normal receive operation takes place when bit 7 of the received data
is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data: bit 7 is “1” and bits 0 to 6
are set to the address of the subordinate microcomputer to be com-
municated with. Then all subordinate microcomputers receive this
data. Each subordinate microcomputer checks the received data,
clears the sleep bit to “0” if bits 0 through 6 are its own address and
sets the sleep bit to “1” if not. Next, the main microcomputer sends
data with bit 7 cleared. Then the microcomputer which cleared the
sleep bit will receive the data, but the microcomputers which set the
sleep bit to “1” will not. In this way, the main microcomputer is able to
communicate only with the designated microcomputer.
Precautions for clock asynchronous (UART)
serial communication
When CTSi and RTSi are separated, pin CLKi cannot be used.
Therefore, when CTSi and RTSi are separated in UART mode, be
sure to select an internal clock.
Before transmit operation is performed, be sure to clear bits 2, 3 and
5 of the serial I/O pin control register (address AC16) to “00”.