參數(shù)資料
型號： M37905M8C-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁數(shù)： 89/105頁
文件大?。?/td> 1040K
代理商： M37905M8C-XXXSP
81
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK GENERATING CIRCUIT
Figure 93 shows the block diagram of the clock generating circuit.
The clock generating circuit consists of the clock oscillation circuit,
PLL frequency multiplier (PLL circuit), system clock switch circuit, pe-
ripheral devices’ clock switch circuit, clock divider, standby control
circuit, etc. As control registers for the clock generating circuit, also,
the clock control register 0 (address BC16), particular function select
register 0 (address 6216) are provided. (See Figures 94 and 95.)
As shown in Figure 93, clocks used in the CPU, BIU, peripheral de-
vices, watchdog timer (in other words, clocks
φCPU, φBIU, f1 to f4096,
Wf32, Wf512) are made from system clock fsys. System clock fsys can
be selected between fXIN (in other words, a clock input from pin XIN)
and fPLL (in other words, an output clock generated by the PLL cir-
cuit.
The PLL circuit’s operation, system clock (fsys) selection, and divi-
sion ratio selection for peripheral devices’ clocks (f1 to f4096) are con-
trolled by the clock control register. The following describes about
these control.
Bit 1 of the clock control register 0 (the PLL circuit operation enable
bit) selects the PLL circuit’s operation (inactive/active). When this bit
is set to “1”, pin VCONT will becomes valid, and the PLL circuit will be
active. At reset, the PLL circuit operation enable bit becomes “1”. (In
this case, the PLL circuit is active.) When not using the PLL circuit,
be sure to clear the PLL circuit operation enable bit to “0” (inactive).
At the STP instruction execution, the PLL circuit is inactive, and pin
VCONT is invalid, regardless of this bit 1’s status.
Bits 2 and 3 of the clock control register (the PLL multiplication ratio
select bits) select the ratio of fPLL/fXIN. The PLL multiplication ratio
must be set so that the frequency of fPLL must be in the range from
10 MHz to 20 MHz. At reset, the PLL multiplication ratio select bits
become “0,1” ( 2). The change of the PLL multiplication ratio must
be performed while input clock fXIN is selected as the system clock.
(In this case, bit 5 of the clock control register 0 = “0”.) After that, be
sure to wait that the operation-stabilizing time of the PLL circuit has
passed, and switch the system clock to fPLL. (In other words, set bit
5 to “1”.) Note that, after reset, the PLL multiplication ratio select bits
are allowed to be changed only once.
Bit 5 of the clock control register 0 is the system clock select bit, and
input clock fXIN is selected as the system clock when bit 5 = “0”. On
the other hand, when bit 5 = “1”, fPLL is selected. At reset, the system
clock select bit becomes “0”. When selecting fPLL, be sure that the
PLL circuit’s operation has fully been stabilized, and then, set the
system clock select bit to “1”. Also, when the PLL circuit operation
enable bit is cleared to “0” (the PLL circuit is inactive.), the system
clock select bit will automatically be cleared to “0”. Note that a value
of “1” cannot be written to the system clock select bit while the PLL
circuit operation enable bit =“0”.
Table 9 lists the fsys selection.
Bits 6 and 7 of the clock control register 0 are the peripheral devices’
clock select bits 0, 1, and these bits select the division ratio of (f1 to
f4096)/(fsys).
Table 10 lists the internal peripheral devices’ operation clock fre-
quency. At reset, these bits become “0, 0”.
Table 9. fsys selection
Table 10. Internal peripheral devices’ operation clock frequency
10 ( 3)
01 ( 2)
System clock fsys
11 ( 4)
fXIN
fPLL
Clock source
Frequency (Note)
Note: The PLL multiplication ratio must be set so that the frequency of fPLL must be in the range from 10 MHz to 20 MHz.
f(XIN) means the frequency of the input clock from pin XIN (fXIN). After reset, the PLL multiplication ratio select bits are allowed to be
changed only once.
PLL circuit operation enable bit
(Bit 1)
System clock select bit
(Bit 5)
1
0
1
f(XIN)
f(XIN) 2
f(XIN) 3
f(XIN) 4
PLL multiplication ratio select bits
(Bits 3, 2) (Note)
fsys/16
fsys/2
Peripheral devices’ clock select bits 1, 0 (bits 7, 6)
fsys/64
fsys
fsys/8
fsys/32
1 0
1 1
Note: When selecting the peripheral devices’ clock select bits 1, 0 = “012”, be sure that system clock fsys does not exceed 10 MHz.
Internal peripheral devices’
operation clock
f1
f16
fsys/2
fsys/4
fsys/32
fsys/128
0 1 (Note)
0 0
f2
f64
f512
f4096
fsys
fsys/512
fsys/4096
fsys/256
fsys/2048
fsys/1024
fsys/8192
Do not select.
相關(guān)PDF資料
PDF描述
M37905M4C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
M37905M4C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
M37905M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
M37905M6C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
M37905M8C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
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