參數(shù)資料
型號(hào)： M37906M6C-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 19/101頁
文件大?。?/td> 766K
代理商： M37906M6C-XXXSP
24
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
cycle while fsys is “H”. However, no sampling pulse is generated until
the cycles whose number is selected by software has passed, even
if the next operation code fetch cycle is generated. The detection of
an interrupt which has the highest priority is performed during that
time.
As shown in Figure 16, there are three different interrupt priority de-
tection time from which one is selected by software. After the se-
lected time has elapsed, the highest priority is determined and is
processed after the currently executing instruction has been com-
pleted.
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E16) shown in Figure 11. Table 6 shows the relationship
between these bits and the number of cycles. After a reset, the pro-
cessor mode register 0 is initialized to “0016.” Therefore, the longest
time is automatically set, however, the shortest time must be se-
lected by software.
Table 5. Value loaded in processor interrupt level (IPL) during an interrupt
Interrupt types
Reset
Watchdog timer
Zero divide
Address matching detection
Setting value
0
7
Not change value of IPL.
Table 6. Relationship between interrupt priority detection time select
bit and number of cycles
Priority detection time select bit
Bit 5
0
1
Bit 4
0
1
0
7 cycles of fsys
4 cycles of fsys
2 cycles of fsys
Number of cycles (Note)
Fig. 16 Interrupt priority detection time
Operation code fetch cycle
fsys
Sampling pulse
Priority detection time
Select one between 00 to
10 with bits 4 and 5 of
processor mode register 0
0 0
0 1
1 0
b5 b4
(Note)
Note: This pulse resides when 2 cycles of fsys is selected.
Note: For system clock fsys, refer to the section on the clock gener-
ating circuit.
相關(guān)PDF資料
PDF描述
M37906M4C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M4C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
M37906M4H-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
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參數(shù)描述
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M37906M8C-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER
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