參數(shù)資料
型號(hào)： M37906M6C-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁(yè)數(shù)： 50/101頁(yè)
文件大?。?/td> 766K
代理商： M37906M6C-XXXSP
52
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 59 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk trans-
mit/receive mode register must be set to “1” and bits 1 and 2 must be
“0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock send-
ing side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk transmit/receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the
clock-sending-side UARTj transmit/receive control register 0. As
shown in Figure 54, the selected clock is divided by (n + 1), then by
2, is passed through a transmission control circuit, and is output as
transmission clock CLKj. Therefore, when the selected clock is fi,
Bit Rate = fi/ {(n + 1)
× 2}
On the clock receiving side, the CS0 and CS1 bits of the UARTk
transmit/receive control register 0 are ignored because an external
clock is selected.
Both of UART0 and UART1 can use CTS and RTS functions.
Bit 4 of the UARTi transmit/receive control register 0 is used to de-
termine whether to use CTS or RTS signal. Bit 4 must be “0” when
CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS sig-
nals are not used. When CTS and RTS signals are not used, CTS/
RTS pin can be used as a normal port pin.
When using pin CTS/RTS, :
If bit 2 of the UARTi transmit/receive control register 0 is cleared to
“0”, CTS input is selected.
If bit 2 is set to “1”, RTS output is selected.
The case using CTS and RTS signals are explained below. As
shown in Figure 66, bits 2 and 3 of the serial I/O pin control register
can determine whether port pins P13 and P17 are used as pins TxDi
or as port pins. When bits 2 and 3 are “0”, P13 and P17 function as
pins TxDi; when bits 2 and 3 are “1”, P13 and P17 function as port
pins. Therefore, in the input-only system where pins TxDi are not
used, pins TxDi can function as port pins.
Fig. 59 Clock synchronous serial communication
UARTj transmit register
TxDj
RxDj
CLKj
CTSj
UARTj transmit buffer register
UARTj receive buffer register
UARTj receive register
UARTj Transmit/Receive mode register
UARTj Transmit/Receive control
register 0
UARTj Transmit/Receive control
register 1
00
0
TX
EPTY
CS1
CS0
RE
RI
OER
FER
PER
CPL
SUM
TI
TE
0
UARTk transmit register
UARTk transmit buffer register
UARTk receive buffer register
UARTk receive register
UARTk Transmit/Receive mode register
UARTk Transmit/Receive control
register 0
UARTk Transmit/Receive control
register 1
01
1
0
1
TX
EPTY
MSB
/LSB
RE
RI
OER
FER
PER
SUM
TI
TE
0
1
TxDk
RxDk
CLKk
RTSk
MSB
/LSB
相關(guān)PDF資料
PDF描述
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