3802 GROUP USER’S MANUAL
3-35
APPENDIX
3.5 List of registers
Fig. 3.5.5 Structure of Serial I/O1 control register
Serial I/O1 synchronous clock
selection bit (SCS)
S
RDY1
output enable bit
(SRDY)
Transmit interrupt
source selection bit (TIC)
Transmit enable bit (TE)
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0 : f(X
IN
)
1 : f(X
IN
)/4
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
0
0
0
Serial I/O1 control register (SIO1CON) [Address : 1A
16
]
Name
BRG count source selection
bit (CSS)
4
5
6
7
0
0
0
0
Serial I/O1 enable bit (SIOE)
0 : I/O port (P4
7
)
1 :
S
RDY1
output pin
0 :
Transmit buffer empty
1 :
Transmit shift operating completion
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : UART
1 : Clock synchronous serial I/O
0 :
Serial I/O1 disabled
(P4
4
–P4
7
:
I/O port)
1 :
Serial I/O1 enabled
(P4
4
–P4
7
:
Serial I/O function pin)
Receive enable bit (RE)
Serial I/O1 mode
selection bit (SIOM)
Fig. 3.5.6 Structure of UART control register
In output mode
0 : CMOS output
1 : N-channel open-drain output
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
UART control register (UARTCON) [Address : 1B
16
]
Name
0
1
1
1
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length
selection bit (STPS)
P4
5
/TxD P-channel
output disable bit (POFF)
5
6
7
4
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “1.”