Rev.1.01
Jan 25, 2005
page 13 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
Fig. 11 Memory map of special function register (SFR)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Serial I/O2 register (SIO2)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
Serial I/O2 control register (SIO2CON)
Interrupt control register 2 (ICON2)
AD conversion register 1 (AD1)
Prescaler Y (PREY)
Timer Y (TY)
AD/DA control register (ADCON)
DA1 conversion register (DA1)
DA2 conversion register (DA2)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Prescaler 12 (PRE12)
Timer 2 (T2)
Prescaler X (PREX)
Timer X (TX)
Timer 1 (T1)
Timer XY mode register (TM)
AD conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Watchdog timer control register (WDTCON)
0FF016
0FF116
Port P0 pull-up control register (PULL0)
Timer Z low-order (TZL)
Timer Z high-order (TZH)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
Timer Z mode register (TZM)
PWM register (PWM)
Baud rate generator 3 (BRG3)
Transmit/Receive buffer register 3 (TB3/RB3)
Serial I/O3 status register (SIO3STS)
Serial I/O3 control register (SIO3CON)
UART3 control register (UART3CON)
Port P1 pull-up control register (PULL1)
0FF216
0FF316
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
0FF416
Port P4 pull-up control register (PULL4)
0FF516
0FF616
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
Reserved area: Do not write any data to these addresses,
because these areas are reserved.
0FE016
0FE116
Flash memory control register 0 (FMCR0)
Flash memory control register 1 (FMCR1)
0FE216
0FE316
Flash memory control register 2 (FMCR2)
Reserved
0FE416
Reserved
0FE516
0FE616
Reserved
0FE716
0FE816
Reserved
0FE916
Reserved
0FEA16
Reserved
0FEB16
0FEC16
Reserved
0FED16
0FEE16
Reserved
0FEF16
Reserved
I2C data shift register (S0)
I2C status register (S1)
I2C control register (S1D)
I2C clock control register (S2)
I2C START/STOP condition control register (S2D)
I2C special mode status register (S3)
I2C special mode control register (S3D)
0FF716
I2C slave address register 0 (S0D0)
0FF816
I2C slave address register 1 (S0D1)
0FF916
I2C slave address register 2 (S0D2)