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193
MITS
UBISHI MICROCOMPUTER
3819 Group
3.3 Control registers
3. APPE NDIX
3819 Group USER’S MANUAL
Fig. 3.3.25 Structure of CPU mode register
Fig. 3.3.26 Structure of Interrupt request register 1
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
1
CPU mode register (CPUM) [Address:3B
16
]
Name
Processor mode bits
Stack page selection bit
0 1 :
1 0 : Not available
1 1 :
0 : 0 page
1 : 1 page
0 : Low
1 : High
5
6
7
0
0
1
Main clock (X
IN
-X
OUT
) stop bit
Main clock division ratio
selection bit
Internal system clock selection
bit
0 : Operating
1 : Stopped
0 : f(X
IN
)/2 (high-speed mode)
1 : f(X
IN
)/8 (middle-speed mode)
0 : X
IN
-X
OUT
selected
(middle/high-speed mode)
1 : X
CIN
-X
COUT
selected
(low-speed mode)
b1b0
0 : I/O port function
1 : X
CIN
–X
COUT
oscillating function
4
Port Xc switch bit
X
COUT
drivability selection bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt request reigster 1 (IREQ1) [Address:3C
16
]
Name
INT
0
interrupt request bit
INT
1
/ZCR interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Serial I/O 1 interrupt request
bit
Serial I/O automatic transfer
interrupt request bit
G
G
6
6
6
6
4
5
6
7
0
0
0
0
Serial I/O 2 interrupt request
bit
Serial I/O 3 interrupt request
bit
Timer 1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
6
6
6
6
6
"0" is set by software, but not "1."
INT
2
interrupt request bit
Remote control/counter
overflow interrupt request bit
G
G