194
3. APPE NDIX
MITS
UBISHI MICROCOMPUTER
3819 Group
3.3 Control registers
3819 Group USER’S MANUAL
Fig. 3.3.28 Structure of Interrupt control register 1
Fig. 3.3.27 Structure of Interrupt request register 2
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
b
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt request reigster 2 (IREQ2) [Address:3D
16
]
Name
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer 6 interrupt request bit
6
6
6
6
5
6
7
0
0
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0."
6
"0" is set by software, but not "1."
FLD blanking interrupt
request bit
FLD digit interrupt request bit
G
G
INT
4
interrupt request bit
A-D conversion interrupt
request bit
G
G
0 : No interrupt request
1 : Interrupt request
6
6
4
0
INT
3
interrupt request bit
6
0
6
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt control register 1 (ICON1) [Address:3E
16
]
Name
INT
0
interrupt enable bit
INT
1
/ZCR interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
4
5
6
7
0
0
0
0
Serial I/O 2 interrupt enable
bit
Serial I/O 3 interrupt enable
bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O 1 interrupt enable
bit
Serial I/O automatic transfer
interrupt enable bit
G
G
INT
2
interrupt enable bit
Remote control/counter
overflow interrupt enable bit
G
G