參數(shù)資料
型號(hào)： M38268MCA-XXXGP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁(yè)數(shù)： 37/95頁(yè)
文件大?。?/td> 1006K
代理商： M38268MCA-XXXGP
Rev.2.00
May. 24, 2006
page 40 of 90
REJ03B0028-0200
3826 Group (A version)
D/A Converter
The 3826 group has a D/A converter with 8-bit resolution and 2
channels (DA1, DA2).
The D/A converter is started by setting the DTMF/DA1 selection bit
and the CTCSS/DA2 selection bit to “0” and setting the value in
the DA conversion register. When the DTMF/DA1 output enable bit
and the CTCSS/DA2 output enable bit is set to “1”, the result of D/
A conversion is output from the corresponding DA1 pin or DA2 pin.
When using the D/A converter, set the P56/DA1 pin and the P57/
DA2 pin to input mode (set “0” to bits 6, 7 of port P5 direction reg-
ister) and the pull-up resistor should be in the OFF state
previously.
The output analog voltage V is determined by the value n (base
10) in the DA conversion register as follows:
V=VREF n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the DA conversion registers are set to “0016”, the DTMF/
DA1 output enable bit and the CTCSS/DA2 output enable bit are
set to “0”, and the P56/DA1 pin and the P57/DA2 pin goes to high
impedance state. The D/A converter is not buffered, so connect an
external buffer when driving a low-impedance load.
■ Note on applied voltage to VREF pin
When the P56/DA1 pin and the P57/DA2 pin are used as an I/O
port, be sure to apply Vcc to VREF pin.
When these pins are used as D/A conversion output pins, the Vcc
level is recommended for the applied voltage to VREF pin.
When the voltage below Vcc level is applied, the D/A conversion
accuracy may be worse.
Fig. 41 Structure of DA control register
Fig. 42 Block diagram of D/A converter
b7
b0
DA control register
(DACON : address 003616)
DTM F/DA1 output enable bit
0 : Disabled
1 : Enabled
CTCSS timer write control bit
0 : Write value in latch only
1 : Write value in latch and counter
High/Low group timer write control bit
0 : Write value in latch only
1 : Write value in latch and counter
High group ROM data selection bit
0 : Sine wave
1 : “0” fixed
Low group ROM data selection bit
0 : Sine wave
1 : “0” fixed
CTCSS/DA2 selection bit
0 : DA2 function
1 : CTCSS function
DTMF/DA1 selection bit
0 : DA1 function
1 : DTMF function
CTCSS/DA2 output enable bit
0 : Disabled
1 : Enabled
P56/DA1
P57/DA2
5-bit adder
Selector
Low
group
ROM
5bit 32
Selector
8-bit timer
XIN/2
CTCSS
ROM
8bit 64
10-bit timer
Selector
High
group
ROM
5bit 32
*
Selector
Data bus
DA1 conversion register (8)
DA1 output enable bit
DA2 output enable bit
Data bus
R-2R resistor ladder
DA2 conversion register (8)
When DTMF is selected, the high-order 6 bits are automatically set as the DTMF output.
The low-order 2 bits is set by writing data to the D-A1 conversion register.
*
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