參數資料
型號: M38268MCA-XXXGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數: 82/95頁
文件大?。?/td> 1006K
代理商: M38268MCA-XXXGP
Rev.2.00
May. 24, 2006
page 81 of 90
REJ03B0028-0200
3826 Group (A version)
3.3.6 Notes on serial I/O1
(1)
Writing to baud rate generator (BRG)
Write data to BRG while the transmission and reception operations are stopped.
(2)
Setting procedure when using serial I/O1 transmit interrupt
When the serial I/O1 transmit interrupt is used, take the following sequence.
Set the serial I/O1 transmit interrupt enable bit (bit 3 of interrupt control register 1 (address 3E16))
to “0” (disabled).
Set the transmit enable bit (bit 4 of serial I/O1 control register (address 1A16)) to “1”.
Set the serial I/O1 transmit interrupt request bit (bit 3 of interrupt request register 1 (address
3C16)) to “0” (no interrupt request issued) after 1 or more instruction has executed.
Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer empty flag (bit 0 of serial I/O1
status register (address 1916)) and the transmit shift register completion flag (bit 2 of serial I/O1
status register) are set to “1”.
Therefore, the serial I/O1 transmit interrupt request bit is set to “1” regardless of the state of the
transmit interrupt source selection bit (bit 3 of serial I/O1 control register).
(3)
Data transmission control with referring to transmit shift register completion flag
After the transmit data is written to the transmit buffer register (address 1816), the transmit shift
register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing the data to the transmit buffer
register, note the delay.
(4)
Setting serial I/O1 control register again
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by setting both the transmit enable bit and the receive enable bit to “0”.
Fig. 3.3.7 Sequence of setting serial I/O1 control register again
Set both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
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