REVISION HISTORY
Rev.
Date
Description
Page
Summary
3826 Group (A version) Data Sheet
1.00 Feb. 18, 2003
1.02 Jul. 31, 2003
First edition issued
Power dissipation revised.
Table 1 Pin description (1) VCC VSS; Function description revised.
Fig.5 Memory expansion plan revised.
Fig.14 Port block diagram (1);
(4) Ports P16, P17,P2, P41, P42 and (5) Port P44 revised.
Fig.15 Port block diagram (2);
(7) Port P46 and (11) Port P54 revised.
Fig.16 Port block diagram (3);
(14) Port P55, (15) Ports P56, P57 and (17) Port P60 revised.
Fig.17 Port block diagram (4);
(19) Port P62 revised.
Fig.40 A-D converter block diagram
Voltage Multiplier (3 Times)
Description of order for operating the voltage multiplier revised.
ROM ORDERING METHOD revised.
Table 16 Recommended operating conditions (4); f(CNTR0) f(CNTR1) revised.
Table 18 Electrical characteristics (2); ICC revised.
Table 19 A-D converter characteristics (1); Note revised.
Table 20 A-D converter characteristics (2); Note revised.
Table 22 Timing requirements (1);
tc(SCLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised.
Table 23 Timing requirements (2);
tc(SCLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised.
Table 25 Switching characteristics (2) ; tr(SCLK1) tf(SCLK1) revised.
Package revised.
Word standardized: “A/D converter”, “D/A converter”, “Serial interface”
FEATURES: A/D converter revised. APPLICATIONS: “household appliances” added.
Fig. 4: Description of RAM added.
Fig. 5: Development status: “under development”
→ “mass production”
Table 3: Date revised.
SFR: AD conversion low-order register (ADL) added to address 001416 and AD
conversion high-order register (ADH) added to address 003516.
A/D CONVERTER: Description revised and ADL added to Fig. 38.
Fig. 39 added and Fig. 40 revised.
Fig. 58: AD conversion low-order register added.
Description revised. Fig. 59: Note added.
Fig. 61: Note 2 added.
Note on Power supply voltage added.
–
1
4
7
18
19
20
21
39
44
58
61
63
64
65
66
67
-
1
6
7
13
38
39
53
54
55
60
2.00 May.24, 2006
(1/2)