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參數(shù)資料
| 型號： | M3826AMFA-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 44/95頁 |
| 文件大?。?/td> | 1006K |
| 代理商： | M3826AMFA-XXXFP |
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Rev.2.00
May. 24, 2006
page 47 of 90
REJ03B0028-0200
3826 Group (A version)
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 49 LCD display RAM map
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
After reset, the VCC (VL3) voltage is output from the common pins.
LCD Display RAM
Addresses 004016 to 005316 are the designated RAM for the LCD
display. When “1” are written to these addresses, the correspond-
ing segments of the LCD display panel are turned on.
LCD Drive Timing
The frequency of internal signal LCDCK decided LCD drive timing
and the frame frequency can be determined with the following
equation:
Table 11 Duty ratio control and common pins used
Duty
ratio
2
3
4
Common pins used
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
Bit 1
0
1
Bit 0
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Duty ratio selection bits
Segment Signal Output Pins
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment or output port pins (SEG18–
SEG25), and the segment or I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset, a VCC (=VL3)
voltage is output to the segment-only pins and the segment/out-
put port pins are the high impedance condition and pulled up to
VCC (=VL3) voltage.
Also, the segment/I/O port pins (SEG26–SEG39) are set to input
mode as I/O ports, and VCC (=VL3) is applied to them by pull-up
resistor.
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
Bit
Address
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
7
6
5
4
3
2
1
0
COM3
COM0
COM2 COM1 COM0 COM3 COM2 COM1
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
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