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參數(shù)資料
| 型號： | M38503E4SS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 32/86頁 |
| 文件大小： | 1193K |
| 代理商： | M38503E4SS |
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32
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 0039
16
) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
0039
16
) and an internal reset occurs at an underflow of the watch-
dog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039
16
) may be
started before an underflow. When the watchdog timer control reg-
ister (address 0039
16
) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
G
Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
0039
16
), each watchdog timer H and L is set to
“
FF
16
.
”
Fig. 35 Structure of Watchdog timer control register
G
Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 0039
16
) per-
mits selecting a watchdog timer H count source. When this bit is
set to
“
0
”
, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(X
IN
)
= 8 MHz frequency and 32.768 s at f(X
CIN
) = 32 kHz frequency.
When this bit is set to
“
1
”
, the count source becomes the signal
divided by 16 for f(X
IN
) (or f(X
CIN
)). The detection time in this case
is set to 512
μ
s at f(X
IN
) = 8 MHz frequency and 128 ms at f(X
CIN
)
= 32 kHz frequency. This bit is cleared to
“
0
”
after reset.
G
Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0039
16
) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is
“
0
”
, the STP instruction is enabled.
When this bit is
“
1
”
, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to
“
1
”
, it cannot be rewritten to
“
0
”
by program. This bit is
cleared to
“
0
”
after reset.
Fig. 34 Block diagram of Watchdog timer
X
I
N
Data bus
X
C
I
N
“
1
0
”
“
0
“
0
0
1
”
”
M
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a
(
N
a
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)
t
“
0
”
“
1
”
1
/
1
6
Watchdog timer H count
source selection bit
R
c
e
r
s
c
e
u
t
t
i
i
S
T
P
i
n
s
t
r
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c
t
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o
n
P
d
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s
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a
t
b
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u
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i
b
o
i
n
t
W
a
t
c
h
d
o
g
t
i
m
e
r
H
(
8
)
“
FF
”
is set when
watchdog timer
control register is
written to.
Internal reset
R
E
S
E
T
Watchdog timer L (8)
Note:
Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
S
T
n
t
“
FF
”
is set when
watchdog timer
control register is
written to.
b
0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
W
0
1
a
W
:
f
t
c
h
a
X
I
d
t
c
N
)
o
h
/
g
d
1
o
6
t
i
g
o
m
e
t
i
r
r
H
e
X
C
I
c
L
N
)
o
u
u
/
1
n
n
6
t
d
s
e
o
r
u
f
l
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c
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s
e
l
e
c
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i
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b
i
t
:
m
f
(
r
o
(
W
a
t
c
h
d
o
g
t
i
m
e
r
H
(
f
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r
r
e
a
d
-
o
u
t
o
f
h
i
g
h
-
o
r
d
e
r
6
b
i
t
)
Watchdog timer control register
(WDTCON : address 0039
16
)
b
7
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