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| 型號(hào)： | M38503E4SS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 37/86頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | M38503E4SS |
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37
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 43 State transitions of system clock
CM
4
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : X
CIN
-X
COUT
oscillating function
CM
5
: Main clock (X
IN
- X
OUT
) stop bit
0 : Operating
1 : Stopped
CM
7
, CM
6
: Main clock division ratio selection bit
b7 b6
0 0 :
φ
= f(X
IN
)/2 ( High-speed mode)
0 1 :
φ
= f(X
IN
)/8 (Middle-speed mode)
1 0 :
φ
= f(X
CIN
)/2 (Low-speed mode)
1 1 : Not available
N
o
t
e
s
R
e
s
e
t
C
M
4
“
1
”
←
“
0
”
C
M
“
0
”
←→
”
←→
“
“
1
”
C
M
6
“
1
0
”
C
M
4
“
1
”
C
←→
M
6
“
1
“
0
”
”
←→
“
0
”
C
M
7
“
1
”
←
“
0
”
C
M
4
“
1
”
←
“
0
”
C
M
5
“
1
”
←
“
0
”
CM
6
“
1
”
←→
“
0
”
C
“
1
M
6
”
←→
“
0
”
CPU mode register
(CPUM : address 003B
16
)
b
7
b
4
C
M
“
0
”
←→
”
←→
“
“
1
”
C
M
6
“
1
0
”
C
C
C
C
M
7
M
6
M
5
M
4
=
=
=
=
0
1
0
0
(
(
8
3
2
M
H
k
H
z
z
o
s
s
t
c
o
i
p
l
l
a
p
t
e
i
n
d
g
)
)
M
i
d
d
(
f
l
(
φ
)
e
-
s
p
=
e
1
e
d
M
H
m
o
)
d
e
z
C
C
C
C
M
7
M
6
M
5
M
4
=
=
=
=
0
1
0
1
(
(
8
3
2
M
H
k
H
z
z
o
o
s
s
c
c
i
l
i
l
l
a
l
a
t
i
t
n
i
n
g
g
)
)
M
i
d
d
(
f
l
(
φ
)
e
-
s
p
=
e
1
e
d
M
H
m
o
)
d
e
z
CM
7
= 0
CM
6
= 0
CM
5
= 0 (8 MHz oscillating)
CM
4
= 0 (32 kHz stopped)
H
i
g
(
h
(
φ
)
-
s
p
=
e
e
4
d
M
m
H
o
z
d
)
e
f
CM
7
= 1
CM
6
= 0
CM
5
= 0 (8 MHz oscillating)
CM
4
= 1 (32 kHz oscillating)
Low-speed mode
(f(
φ
)=16 kHz)
C
C
C
C
M
7
M
6
M
5
M
4
=
=
=
=
1
0
1
1
(
(
8
3
2
M
H
k
H
z
z
s
t
o
s
p
c
p
i
l
e
l
a
d
t
)
n
o
i
g
)
L
o
w
(
f
-
s
p
=
e
1
e
6
d
k
m
H
o
z
d
)
e
(
φ
)
CM
7
= 0
CM
6
= 0
CM
5
= 0 (8 MHz oscillating)
CM
4
= 1 (32 kHz oscillating)
High-speed mode
(f(
φ
) = 4 MHz)
1 :
Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 :
The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 :
Timer operates in the wait mode.
4 :
When bit 0 of MISRG is
“
0
”
and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed
mode.
5 :
When bit 0 of MISRG is
“
0
”
and the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is
“
0
”
.
(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is
“
1
”
.
6 :
Wait until oscillation stabilizes after oscillating the main clock X
IN
before the switching from the low-speed mode to middle/high-speed
mode.
7 :
The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin.
φ
indicates the internal clock.
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