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參數(shù)資料
| 型號(hào)： | M3851 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機(jī)) |
| 中文描述： | 單芯片8位單片機(jī)（8位單片機(jī)） |
| 文件頁數(shù)： | 27/61頁 |
| 文件大?。?/td> | 904K |
| 代理商： | M3851 |
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27
3851 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I
2
C START/STOP Condition Control Register
(S2D)] 0030
16
The I
2
C START/STOP condition control register (address 0030
16
)
controls START/STOP condition detection.
Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(X
IN
) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 8.
Do not set “00000
2
” or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
Refer to Table 9, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note:
When changing the setting of the S
CL
/S
DA
interrupt pin polarity se-
lection bit, the S
CL
/S
DA
interrupt pin selection bit, or the I
2
C-BUS
interface enable bit ES0, the S
CL
/S
DA
interrupt request bit may be
set. When selecting the S
CL
/S
DA
interrupt source, disable the inter-
rupt before the S
CL
/S
DA
interrupt pin polarity selection bit, the S
CL
/
S
DA
interrupt pin selection bit, or the I
2
C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I
2
C control register (address 002E
16
) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I
2
C address register
(address 002C
16
). At the time of this comparison, address com-
parison of the RWB bit of the I
2
C address register (address
002C
16
) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 31,
(1) and (2).
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I
2
C control register (address 002E
16
) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I
2
C address register (address 002C
16
). At the time of this
comparison, an address comparison between the RWB bit of
the I
2
C address register (address 002C
16
) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I
2
C status register (address 002D
16
) is set to
“1.” After the second-byte address data is stored into the I
2
C
data shift register (address 002B
16
), perform an address com-
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RBW bit of the I
2
C address register
(address 002C
16
) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I
2
C address register (address 002C
16
). For the data trans-
mission format when the 10-bit addressing format is selected,
refer to Figure 31, (3) and (4).
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