參數(shù)資料
型號(hào)： M38857M8-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 45/105頁(yè)
文件大?。?/td> 1403K
代理商： M38857M8-XXXHP
41
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
+ 2 cycles (3.375
s)
+ 1 cycle < 4.0
s (3.25 s)
Fig. 39 START condition detecting timing diagram
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 39, 40, and Table 14. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 14).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 14, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I2CIRQ” occurs to the CPU.
Table 14 START condition/STOP condition detecting conditions
Note: Unit : Cycle number of system clock
φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at
φ = 4 MHz.
Fig. 40 STOP condition detecting timing diagram
SCL release time
Standard clock mode
High-speed clock mode
4 cycles (1.0
s)
2 cycles (1.0
s)
2 cycles (0.5
s)
3.5 cycles (0.875
s)
SSC value
2
SSC value
2
SSC value –1
2
Setup time
Hold time
BB flag set/
reset time
SSC value + 1 cycle (6.25
s)
cycle < 4.0
s (3.0 s)
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (S1) at the same time after writing the slave address to
the I2C data shift register (S0) with the condition in which the ES0
bit of the I2C control register (S1D) and the BB flag are “0”, a
START condition occurs. After that, the bit counter becomes
“0002” and an SCL for 1 byte is output. The START condition gen-
erating timing is different in the standard clock mode and the
high-speed clock mode. Refer to Figure 37, the START condition
generating timing diagram, and Table 12, the START condition
generating timing table.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (S1D) is “1”, write “1”
to the MST and TRX bits, and write “0” to the BB bit of the I2C sta-
tus register (S1) simultaneously. Then a STOP condition occurs.
The STOP condition generating timing is different in the standard
clock mode and the high-speed clock mode. Refer to Figure 38,
the STOP condition generating timing diagram, and Table 13, the
STOP condition generating timing table.
Fig. 37 START condition generating timing diagram
Fig. 38 STOP condition generating timing diagram
Table 13 STOP condition generating timing table
Item
Setup
time
START/STOP condition
generating selection bit
“0”
“1”
“0”
“1”
Standard
clock mode
5.5
s (22 cycles)
13.5
s (54 cycles)
5.5
s (22 cycles)
13.5
s (54 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed
clock mode
3.0
s (12 cycles)
7.0
s (28 cycles)
3.0
s (12 cycles)
7.0
s (28 cycles)
Table 12 START condition generating timing table
Item
Setup
time
START/STOP condition
generating selection bit
Standard
clock mode
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed
clock mode
“0”
“1”
“0”
“1”
5.0
s (20 cycles)
13.0
s (52 cycles)
5.0
s (20 cycles)
13.0
s (52 cycles)
2.5
s (10 cycles)
6.5
s (26 cycles)
2.5
s (10 cycles)
6.5
s (26 cycles)
Hold
time
Hold
time
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
Hold time
Setup
time
SCL
SDA
BB flag
SCL release time
BB flag
reset
time
Hold time
Setup
time
SCL
SDA
BB flag
SCL release time
BB flag
reset
time
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