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參數(shù)資料
| 型號： | M38857M8-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 57/105頁 |
| 文件大?。?/td> | 1403K |
| 代理商： | M38857M8-XXXHP |
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3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
52
Basic Operation of LPC Interface
Set up steps for LPC interface is as below.
Set the LPC interface enable bit (bit3 of LPCCON) to “1”.
Choose which data bus buffer channel use.
Set the data bus buffer i enable bit (i = 0, 1) (bit 4 or 5 of
LPCCON) to “1”.
Set the slave address to LPCi address register L and H (i = 0, 1)
(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH).
(1) Example of I/O write cycle
The I/O write cycle timing is shown in Figure 48. The standard
transfer cycle number of I/O write cycle is 13. The communication
starts from the falling edge of LFRAME.
The data on LAD [3:0] is monitored at every rising edge of LCLK.
1st clock: The last clock when LFRAME is “Low”. The host send
“00002” on LAD [3:0] for communication start.
2nd clock: LFRAME is “High”. The host send “001X2” on LAD
[3:0] to inform the cycle type as I/O write.
From 3rd clock to 6th clock : In these four cycles , the host sends
16-bit slave address. The 3885 compares it with the LPCi ad-
dress register H and L (i = 0, 1).
3rd clock: The slave address bit [15:12].
4th clock: The slave address bit [11:8].
5th clock: The slave address bit [7:4].
6th clock: The slave address bit [3:0].
7th clock and 8th clock are used for one data byte transfer. The
data is written to the input data bus buffer (DBBINi, i = 0, 1)
7th clock: The host sends the data bit [3:0].
8th clock: The host sends the data bit [7:4].
9th clock and 10th clock are for turning the communication direc-
tion from the host
→the peripheral to the slave→the host.
9th clock: The host outputs “11112” on LAD [3:0].
10th clock: The LAD [3:0] is set to tri-state by the host to
turn the communication direction.
11th clock: The 3885 outputs “00002” (SYNC OK) to LAD [3:0] for
acknowledgment.
12th clock: The 3885 outputs “11112” to LAD [3:0]. In this timing
the address bit 2 is latched to XA2i (bit3 of DBBSTSi),
IBFi (bit 1 of DBBSTSi) is set to “1” and IBF interrupt
signal is generated.
13th clock: The LAD [3:0] is set to tri-state by the host to turn the
communication direction.
(2) Example for I/O read cycle
The I/O read cycle timing is shown in Figure 49. The standard
transfer cycle number of I/O read cycle is 13. The data on LAD
[3:0] is monitored at every rising edge of LCLK. The communica-
tion starts from the falling edge of LFRAME.
1st clock: The last clock when LFRAME is “Low”. The host sends
“00002” on LAD [3:0] for communication start.
2nd clock: LFRAME is “High”. The host sends “000X2” on LAD
[3:0] to inform the cycle type as I/O read.
From 3rd clock to 6th clock: In these four cycles , the host sends
16-bit slave address. The 3885 compares it with the LPCi ad-
dress register H or L (i = 0, 1).
3rd clock: The slave address bit [15:12].
4th clock: The slave address bit [11:8].
5th clock: The slave address bit [7:4].
6th clock: The slave address bit [3:0].
7thclock and 8thclock are used for turning the communication di-
rection from the host
→the peripheral to the peripheral→the host.
7th clock: The host outputs “11112” on LAD [3:0].
8th clock: The LAD [3:0] is set to tri-state by the host to
turn the communication direction.
9th clock: The 3885 outputs “00002” (SYNC OK) to LAD [3:0] for
acknowledgment.
10th clock and 11th clock are used for one data byte transfer from
the output data bus buffer i (DBBOUTi) or data bus buffer status
register i (DBBSTSi).
10th clock: The 3885 sends the data bit [3:0].
11th clock: The 3885 sends the data bit [7:4].
12th clock: The 3885 outputs “11112” to LAD [3:0]. In this timing
OBFi (bit 2 of DBBSTSi) is cleared to “0” and OBE
interrupt signal is generated.
13th clock: The LAD [3:0] is set to tri-state by the host to turn the
communication direction.
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