38B5 Group User’s Manual
APPLICATION
2-81
2.3 Serial I/O
(2)
Notes when selecting clock asynchronous serial I/O
Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
q Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
q Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3)
SRDY2 output of reception side
When signals are output from the SRDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4)
Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Fig. 2.3.56 Sequence of setting serial I/O2 control register again
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time