Rev.3.02
Apr 10, 2008
REJ03B0177-0302
38D2 Group
Fig. 25 Structure of timer 1 to timer 4 related registers
Timer 12 mode register
(T12M: address 002516)
Timer 34 mode register
(T34M: address 002616)
Timer 1234 mode register
(T1234M: address 002716)
Timer 1234 frequency division selection register
(PRE1234: address 002816)
PWM01 register
(PWM01: address 002416)
Timer 1 frequency division selection bits
b1b0
0 0 : 1/16
× φ SOURCE
0 1 : 1/1
× φ SOURCE
1 0 : 1/2
× φ SOURCE
1 1 : 1/256
× φ SOURCE
Timer 3 frequency division selection bits
b5b4
0 0 : 1/16
× φSOURCE
0 1 : 1/1
× φ SOURCE
1 0 : 1/2
× φ SOURCE
1 1 : 1/256
× φ SOURCE
Timer 1 count stop bit
0 : Count operation
1 : Count stop
T2OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 2 output selection bit (P36)
0 : I/O port
1 : Timer 2 output
Timer 2 count source selection bits
b5b4
0 0 : Underflow of timer 1
0 1 : f(XCIN)
1 0 : Frequency divider for timer 2
1 1 : Not available
Timer 1 count source selection bits
b3b2
0 0 : Frequency divider for timer 1
0 1 : f(XCIN)
1 0 : Underflow of timer Y
1 1 : Not available
Timer 2 count stop bit
0 : Count operation
1 : Count stop
PWM0 set bits
b1b0
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
Not used (returns “0” when read)
PWM1 set bits
b3b2
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
Timer 2 frequency division selection bits
b3b2
0 0 : 1/16
× φ SOURCE
0 1 : 1/1
× φ SOURCE
1 0 : 1/2
× φ SOURCE
1 1 : 1/256
× φ SOURCE
Timer 4 frequency division selection bits
b7b6
0 0 : 1/16
× φ SOURCE
0 1 : 1/1
× φ SOURCE
1 0 : 1/2
× φ SOURCE
1 1 : 1/256
× φ SOURCE
T3OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Not used (returns “0” when read)
Timer 4 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 3 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 4 output selection bit (P53)
0 : I/O port
1 : Timer 4 output
Timer 3 output selection bit (P52)
0 : I/O port
1 : Timer 3 output
T4OUT output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Not used (returns “0” when read)
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 4 count source selection bits
b4b3
0 0 : Frequency divider for timer 4
0 1 : Underflow of Timer 3
1 0 : Underflow of Timer 2
1 1 : f(XIN)
Timer 3 count source selection bit
0 : Frequency divider for timer 3
1 : Underflow of Timer 2
Timer 4 count stop bit
0 : Count operation
1 : Count stop
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
Note1:
φSOURCE indicates the followings:
XIN input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)