參數(shù)資料
型號(hào): M38D24G6HP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝: 10X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù): 80/138頁(yè)
文件大小: 2880K
代理商: M38D24G6HP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)當(dāng)前第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)
Rev.3.02
Apr 10, 2008
Page 44 of 131
REJ03B0177-0302
38D2 Group
A/D CONVERTER
The 38D2 Group has a 10-bit A/D converter. The A/D converter
performs successive approximation conversion. The 38D2 Group
has the ADKEY function which perform A/D conversion of the
“L” level analog input from the ADKEY pin automatically.
[AD Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the AD conversion register (high-order) (address
001716), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the AD conversion register (low-order) (address
001616).
During A/D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference
voltage input pin (VREF) can be controlled by the VREF input
switch bit (bit 0 of address 001616). When “1” is written to this
bit, the resistor ladder is always connected to VREF. When “0” is
written to this bit, the resistor ladder is disconnected from VREF
except during the A/D conversion.
[AD Control Register (ADCON)]
This register controls A/D converter. Bits 2 to 0 are analog input
pin selection bits. Bit 3 is an AD conversion completion bit and
“0” during A/D conversion. This bit is set to “1” upon
completion of A/D conversion.
A/D conversion is started by setting “0” in this bit.
Bit 5 is the ADKEY enable bit. The ADKEY function is enabled
by setting “1” to this bit. When this function is valid, the analog
input pin selection bits are ignored. Also, when bit 5 is “1”, do
not set “0” to bit 3 by program.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P47/AN7
P40/AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compare an analog input
voltage with the comparison voltage and store the result in the
AD conversion register. When an A/D conversion is completed,
the control circuit sets the AD conversion completion bit and the
AD conversion interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The
conversion accuracy may be low because the change is lost if the
conversion speed is not enough.
Accordingly, set f(XIN) to at least 500 kHz during A/D
conversion in the XIN mode.
Also, do not execute the STP and WIT instructions during the
A/D conversion.
In the low-speed mode and on-chip oscillator mode, there is no
limit on the oscillation frequency because the on-chip oscillator
is used as the A/D conversion clock. In the low-speed mode, on-
chip oscillator starts oscillation automatically at the A/D
conversion is executed and stops oscillation automatically at the
A/D conversion is finished even though it is not oscillating.
Fig. 36 Block diagram of A/D converter
(Address 001716)
(Address 001616)
ADKEY
control circuit
A/D control circuit
AVSS
b7
b0
Data bus
C
ha
nn
el
se
le
cto
r
AD conversion register (H)
Resistor ladder
Comparator
A/D interrupt request
AD control register
P40/AN0
P41/AN1
P42/AN2/ADKEY
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
AD conversion register (L)
VREF
1/8
1/2
φ
SOURCE
Note: In frequency/2, frequency/4, or frequency/8 mode, φSOURCE is the XIN input.
In low-speed mode, or on-chip oscillator mode, φSOURCE is the on-chip
oscillator frequency divided by 4.
相關(guān)PDF資料
PDF描述
M38D24G4FP 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
M38D24G4-XXXHP 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
M38D28G8HP 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
M38D29FFHP 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
M38D24G6FP 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M38D24G6HP#U0 功能描述:IC 740/38D2 MCU QZ-ROM 64LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI,I²C,UART/USART 外圍設(shè)備:POR,PWM,WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC(J 形引線(xiàn)) 包裝:帶卷 (TR)
M38D24G6XXXFP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38D24G6XXXHP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38D24G7XXXFP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38D24G7XXXHP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER