參數(shù)資料
型號： M38D24G6HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝： 10X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 82/138頁
文件大小： 2880K
代理商： M38D24G6HP
Rev.3.02
Apr 10, 2008
Page 46 of 131
REJ03B0177-0302
38D2 Group
LCD DRIVE CONTROL CIRCUIT
The 38D2 Group has the built-in Liquid Crystal Display (LCD)
drive control circuit consisting of the following.
LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 24 segment output pins and 4 common output
pins can be used.
Up to 96 pixels can be controlled for an LCD display. When the
LCD enable bit is set to “1” after data is set in the LCD mode
register, the segment output disable register, and the LCD display
RAM, the LCD drive control circuit starts reading the display
data automatically, performs the bias control and the duty ratio
control, and displays the data on the LCD panel.
.
Fig. 38 Structure of LCD related registers
Table 11
Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixels
2
48 dots
or 8 segment LCD 6 digits
3
72 dots
or 8 segment LCD 9 digits
4
96 dots
or 8 segment LCD 12 digits
LCD mode register
(LM : address 001316)
b7
b0
Duty ratio selection bits
b1b0
0 0 : Not used
0 1 : 2 (use COM0, COM1)
1 0 : 3 (use COM0-COM2)
1 1 : 4 (use COM0-COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : Type A
1 : Type B
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note 3)
0 : f(XCIN)/32
1 :
φSOURCE/8192
Segment output disable register 0
(SEG0 : address 0FF416)
b7
b0
Segment output disable bit 0
0 : Segment output SEG0
1 : Output port P00
Segment output disable bit 1
0 : Segment output SEG1
1 : Output port P01
Segment output disable bit 2
0 : Segment output SEG2
1 : Output port P02
Segment output disable bit 3
0 : Segment output SEG3
1 : Output port P03
Segment output disable bit 4
0 : Segment output SEG4
1 : Output port P04
Segment output disable bit 5
0 : Segment output SEG5
1 : Output port P05
Segment output disable bit 6
0 : Segment output SEG6
1 : Output port P06
Segment output disable bit 7
0 : Segment output SEG7
1 : Output port P07
Segment output disable register 1
(SEG1 : address 0FF516)
b7
b0
Segment output disable bit 8
0 : Segment output SEG8
1 : Output port P10
Segment output disable bit 9
0 : Segment output SEG9
1 : Output port P11
Segment output disable bit 10
0 : Segment output SEG10
1 : Output port P12
Segment output disable bit 11
0 : Segment output SEG11
1 : Output port P13
Segment output disable bit 12
0 : Segment output SEG12
1 : Output port P14
Segment output disable bit 13
0 : Segment output SEG13
1 : Output port P15
Segment output disable bit 14
0 : Segment output SEG14
1 : Output port P16
Segment output disable bit 15
0 : Segment output SEG15
1 : Output port P17
Segment output disable register 2
(SEG2 : address 0FE616)
b7
b0
Segment output disable bit 16
0 : Segment output SEG16
1 : Output port P20
Segment output disable bit 17
0 : Segment output SEG17
1 : Output port P21
Segment output disable bit 18
0 : Segment output SEG18
1 : Output port P22
Segment output disable bit 19
0 : Segment output SEG19
1 : Output port P23
Segment output disable bit 20
0 : Segment output SEG20
1 : Output port P24
Segment output disable bit 21
0 : Segment output SEG21
1 : Output port P25
Segment output disable bit 22
0 : Segment output SEG22
1 : Output port P26
Segment output disable bit 23
0 : Segment output SEG23
1 : Output port P27
Notes 1: Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable
register.
2: When the VL pin input selection bit (VLSEL) of the LCD power control register (address 003816) is “1”, settings of the segment output disable bit 22 and
segment output disable bit 23 are invalid.
3: LCDCK is a clock for an LCD timing controller.
φ SOURCE represents the supply source of internal clock φ.
XIN input: in the frequency/2, 4 or 8 mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode.
(1)
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M38D24G6HP#U0 功能描述:IC 740/38D2 MCU QZ-ROM 64LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR)
M38D24G6XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38D24G6XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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