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參數(shù)資料
| 型號： | M40Z111MH6TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| 中文描述： | 5V或3V NVRAM中的主管，直到兩名LPSRAMs |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 114K |
| 代理商： | M40Z111MH6TR |
7/15
M40Z111, M40Z111W
OPERATION
The M40Z111/W, as shown in Figure 4, page 4,
can control up to two standard low-power SRAMs.
These SRAMs must be configured to have the
chip enable input disable all other input signals.
Most slow, low-power SRAMs are configured like
this, however many fast SRAMs are not. During
normal operating conditions, the conditioned chip
enable (E
CON
) output pin follows the chip enable
(E) input pin with timing shown in Table 6, page 9.
An internal switch connects V
CC
to V
OUT
. This
switch has a voltage drop of less than 0.3V
(I
OUT1
).
When V
CC
degrades during a power failure, E
CON
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
as V
CC
falls below an out-of-tolerance threshold
(V
PFD
). The power fail detection value associated
with V
PFD
is selected by the THS pin and is shown
in Table 5, page 6.
Note:
The THS pin must be connected to either
V
SS
or V
OUT
.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
WP
,
E
CON
is unconditionally driven high, write protect-
ing the SRAM.
A power failure during a write cycle may corrupt
data at the currently addressed location, but does
not jeopardize the rest of the SRAM's contents. At
voltages below V
PFD
(min), the user can be as-
sured the memory will be write protected provided
the V
CC
fall time exceeds t
F
.
As V
CC
continues to degrade, the internal switch
disconnects V
CC
and connects the internal battery
to V
OUT
. This occurs at the switchover voltage
(V
SO
). Below the V
SO
, the battery provides a volt-
age V
OHB
to the SRAM and can supply current
I
OUT2
(see Table 5, page 6). When V
CC
rises
above V
SO
, V
OUT
is switched back to the supply
voltage. Output E
CON
is held inactive for t
ER
(200ms maximum) after the power supply has
reached V
PFD
, independent of the E input, to allow
for processor stabilization (see Figure 7, page 8).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40Z111/W NVRAM SUPERVI-
SOR. There are, however some criteria which
should be used in making the final choice of which
SRAM to use. The SRAM must be designed in a
way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the
M40Z111/W and SRAMs to be “Don't Care” once
V
CC
falls below V
PFD
(min). The SRAM should
also guarantee data retention down to V
CC
= 2.0V.
The chip enable access time must be sufficient to
meet the system needs with the chip enable prop-
agation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
tied to V
OUT
. If data retention lifetime is a critical
parameter for the system, it is important to review
the data retention current specifications for the
particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
Manufacturers generally specify a typical condi-
tion for room temperature along with a worst case
condition (generally at elevated temperatures).
The system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
the I
CCDR
value of the M40Z111/W to determine
the total current requirements for data retention.
The available battery capacity for the SNAPHAT
of your choice can then be divided by this current
to determine the amount of data retention avail-
able (see Table 8, page 10). For more information
on Battery Storage Life refer to the Application
Note AN1012.
相關(guān)PDF資料 |
PDF描述 |
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| M40Z111WMH6 | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111WMH6TR | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111 | NVRAM Controller for up to Two LPSRAM(NVRAM控制器) |
| M40Z300AV | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300AVMH1E | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M40Z111SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to two LPSRAMs |
| M40Z111WMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111WMH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111WMH6E | 功能描述:監(jiān)控電路 N-Ch, 5V or 3V NVRAM up to 2 LPSRAMs RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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